A new technique to measure the electron drift mobility, µD, in n-type doped a-Si:H is described. µD is defined from the d. c. conductivity, σ, and the density of electrons in the band tail, nBT, by the expression σ = nBT e µD. The temperature dependence of the mobility was measured from 200K to 450K for both the thermal equilibrium and the frozen in states at different doping levels, using sweep out measurements to obtain nBT for the same thermal conditions. Doping up to 10-2 PH3/SiH4 suppresses µD by about an order of magnitude at room temperature, and increases its activation energy. Numerical modelling shows that a shift of the mobility edge into the conduction band by about 100 meV gives the best fit to the data, and is attributed to potential fluctuations induced by charged dopant and defect states.

A vertical amorphous silicon thin-film transistor that has a very short channel length that is determined by deposition, not lithography, is described. These transistors have a field-effect mobility of approximately 0.5 cm2 /V s, an effective channel length of 1.5 μm, and a dynamic range of over five orders of magnitude. A method for suppressing excessive leakage currents and improving the saturation of the output characteristics by a novel current-blocking technique is shown. A two-dimensional computer program is used to analyze these devices and guide their design and optimization. Unlike a conventional thin-film transistor, the current path is primarily parallel to the electric field created by an insulated gate electrode. These vertical transistors are easy to fabricate, compatible with large-area processing techniques, and have suitable terminal characteristics for use in practical circuits.

In this paper we describe a new analytic model for both the current-voltage and capacitance-voltage characteristics of amorphous-silicon thin-film transistors. This analytic model has been incorporated into a circuit simulation program (SPICE) to provide an accurate comprehensive three terminal model for amorphous-silicon thin-film transistors. We present results showing good agreement between circuit simulations based on this new device model and experimental data. The development of amorphous silicon SPICE simulation tools increases the design accuracy of advanced analog and digital circuits.

Whereas one-dimensional models can adequately predict the current-voltage behavior of ideal thin-film transistors, a detailed study of current flow requires a comprehensive two-dimensional simulation. Such an analysis provides important information regarding effective series resistance, overlap capacitance, and currentcrowding near electrodes. Numerical simulations also allow the rapid development and optimization of new devices. We have developed a two-dimensional finite-element device simulator (MANIFEST) which we have used to study the effect of source-to-gate misalignments on the performance of amorphous-silicon TFTs. We find that submicron source-togate gaps do not seriously impair TFT performance.

We present experimental results on the transient response of the source-drain current of laser crystallised polycrystalline silicon (poly-Si) thin film transistors (TFTs) over many orders of magnitude in time after the application of a voltage pulse to the gate electrode. This work follows on from similar measurements performed on amorphous silicon (a-Si) TFTs. Results showed a definite change in transient behaviour dependent on the magnitude of the gate bias. At a gate voltage of 5V there was an initial decay then a marked increase in the source-drain current beyond 1000 seconds. This variation of transient behaviour with gate bias was not seen in the a-Si case. For poly-Si the transient behaviour could not be split into different regimes in time (beyond the carrier transit time) whereas for a-Si TFTs the source-drain current showed a logarithmic decay at room temperature up to 100 seconds followed by a power law decay beyond 100 seconds. Our results indicate perhaps that only one mechanism exists for the observed transient decay of current, unlike the a-Si case. Measurements carried out at elevated temperature showed the current decay was independent of temperature indicating that the transient decay may be caused by charge injection via a tunnelling process into interface states, gate dielectric or passivation dielectric. Finally by carrying out measurements on TFTs after moderate positive voltage stressing and on TFTs with specially fabricated gate and passivation dielectrics it has been established that the transient decay is dielectric related and not a defect generation process.

We propose a new general principle of operation for solid-state devices, and demonstrate a novel transistor which we call a double-injection field-effect transistor, based on this principle. We have fabricated amorphous silicon alloy double-injection transistors operating on the modulation of a double-injection current by a gate field covering the complete path of the current channel. Using these amorphous silicon alloy double-injection transistors, we have achieved currents over 20 times those theoretically possible for conventional amorphous silicon field-effect transistors operating under similar conditions. This new principle, applicable to both thin-film amorphous and crystalline devices, offers the potential of high-current, high-speed field-effect transistors with modulated optical emission.

In this paper we describe the design and operation of two novel types of amorphous silicon thin-film transistors and outline their application in large-area microelectronics. We first consider a high voltage transistor that can modulate a source-drain voltage in excess of 400 volts by applying low voltages to a controlling electrode covering a small portion of the channel near to the source. Secondly, for high-current output and moderately high voltage applications, we have fabricated vertical amorphous silicon transistors with channel lengths much smaller than the lithographic minimum feature size used in their fabrication. We show the design of both these new transistors together with their physics of operation and give results of output characteristics. The integration of low and high voltage transistors into large-area circuits has enabled us to develop new applications for amorphous silicon in printing, input scanning and electronic copying. Page-wide arrays of both ionographic and electrographic printers have been fabricated. By combining amorphous silicon photodiodes with transistor arrays, we have made high resolution document scanners and copiers with directly coupled print and sensor elements. The ability to fabricate short channel vertical transistors offers the potential to further increase the speed and resolution of these large-area circuits.

In this paper we describe the operation of a novel amorphous silicon high voltage transistor. Its attractive feature is that it can operate at source-drain voltages in excess of 400 volts but its characteristics are controlled by applying only a low bias (0-10 volts) to a gate electrode covering a small portion of the sourcedrain channel near to the source. The portion of the device over this gate electrode operates as a conventional amorphous silicon Field-Effect Transistor which injects electrons into the intrinsic amorphous silicon between this region and the drain electrode. We present experimental data showing the current-voltage characteristics of this new transistor as a function of geometry and demonstrate that the above model realistically describes its operation.

On the basis of our experimental studies of the temperature dependence of amorphous silicon thin film transistor current-voltage and capacitance-voltage characteristics, we have developed an analytical device model suitable for implementation in circuit simulators. This model describes the above-threshold (on) current and the subthreshold (off) current [1]. In addition, the model is able to incorporate changes in the distribution of localized states which arise from thermal and/or bias stress. In this paper, we identify the temperature-dependent parameters, which describe the temperature dependence of both the on and off currents, and we model the leakage current at large negative gate biases. The modeling results are in good agreement with our experimental data. We also discuss capacitance-voltage characteristics of amorphous silicon thin film transistors for varying gate lengths, temperatures, and frequencies. The measured capacitance-voltage characteristics show strong frequency dispersion, which is related to the trap-limited transport of carriers in the channel. The characteristic time constant, which determines when the channel capacitance becomes dependent on frequency, is on the order of the transit time calculated with the field-effect mobility and the electric field. The field-effect mobility takes into account carrier trapping by the localized states and is a function of gate voltage and temperature.

In this paper we develop a new theory to describe the characteristics of amorphous silicon based alloy field-effect transistors. We show that the transition from below to above threshold operation occurs when the Fermi level in the accumulation region moves from the deep to tail localized states in the energy gap. The current-voltage and capacitance-voltage characteristics are related to the basic material parameters such as the distribution of localized states in the energy gap, band mobility, device geometry, channel doping, and series resistances. Our analysis shows that an on current in excess of 2×10−7 A/μm gate width can be obtained with a 10-μm gate length. We also demonstrate that even in the above threshold regime the field-effect mobility is dependent on the gate voltage. Our theory can be used to optimize the design of amorphous silicon based alloy field-effect transistors.

A semi-empirical analytical model for the DC characteristics of both n- and p-channel polysilicon thin-film transistors is described. The model is suitable for implementation in a SPICE circuit simulator, Our semi-empirical approach results in a physically based model with a minimum of parameters, which are readily related to the device structure and fabrication process. The intrinsic DC model describes all four regimes of operation: leakage, subthreshold, above threshold, and kink, The effects of temperature and channel length are also included in the short-channel model.

Distinct features of amorphous and polycrystalline silicon are attractive for large-area electronics. These features can be utilized in a hybrid structure which consists of both amorphous and polycrystalline silicon materials. For example, an extension of active matrix technology is the integration of peripheral drivers for the improvement of reliability, cost reduction and compactness of the packaging for large-area electronics. This goal can be approached by a combination of amorphous silicon pixel switches and polysilicon drivers. A monolithic fabrication process has been developed based on a simple modification of the amorphous silicon transistor process which uses selective area laser crystallization. This approach allows us to share many of the process steps involved in making both the amorphous and polysilicon devices. Another example of the hybrid device structure is a self-aligned amorphous silicon thin film transistor with polysilicon source and drain contacts. The advantages of the self-aligned transistor are reduction of the parasitic capacitance and scaling down of the device dimension. With a selective laser doping technique, self-aligned and short-channel amorphous silicon thin film transistors have been demonstrated.

We present an analytical SPICE model for the AC and DC characteristics of n and p channel polysilicon TFTs which scales fully with channel length and width in all regimes of operation (leakage, subthreshold, above threshold, and kink) and accounts for the frequency dispersion of the capacitance. Once physically based parameters have been extracted from long channel TFTs, which include the gate length and drain bias dependencies of the device parameters, our model accurately reproduces short channel device characteristics. The AC model includes the input channel resistance in series with the gate oxide capacitance. As a result, our model is able to fit the frequency dispersion of the device capacitances. The model has been implemented in the AIM-Spice simulator and good agreement is observed between measured and modeled results for gate lengths down to 4 mu m.

Based on experimental and theoretical studies of n- and p-channel polysilicon thin film transistors with gate W/L ratios from 0.3 to 3.3, we have demonstrated that the threshold voltage extracted from gate to channel capacitance data results in field effect mobility parameters which are independent of device geometry. The parameters extracted using this V/sub t/ allow us to reproduce the I-V characteristics of the n- and p channel TFTs over wide ranges of bias voltages and gate sizes. The C/sub gc/-V/sub GS/ characteristics of polysilicon TFTs are strongly affected by the trapping and de-trapping of carriers. As a result, the measured C/sub gc/ characteristic is a function of measurement frequency and gate length. However, we demonstrate that to the first order, the frequency dispersion of the C/sub gc/ curve can be related to the effective carrier transit time determined using the V/sub GS/ dependent field effect mobility.