The demand for prehospital emergency care has increased during the last decades throughout the Western world, in terms of numbers of emergency calls and dispatched ambulances. This development represents a challenge for both the prehospital emergency systems and the emergency departments at the hospitals [1]. Stroke is the fourth single leading cause of death in the UK and an accurate recognition of stroke by in-ambulance or emergency medical services (EMS) or prehospital ambulance paramedics, offers significant potential to reduce delays in presentation and treatment in acute stroke [2]. This paper demonstrates Proof-of-Concept (PoC) approaches for 5G network slicing in mission-critical use cases from the H2020 5G PPP SliceNet project, which is implementing an End-to-End (E2E) cognitive network slicing and slice management framework in virtualised multi-domain, multi-tenant 5G Networks. The paper shows how the PoC's key enablers, such as QoS-aware network slicing, edge computing and hardware acceleration, can assist with a continuous collection, processing and streaming of patient data that could shorten the time to assess and provide optimal clinical treatment pathways for potential stroke patients.

Affective Computing is a rather new and multidisciplinary research field that seeks sophisticated automation in emotion detection for later analysis. However, the automated emotion detection and analysis require as well comprehensive data management support, e.g. to keep control of data produced, and to enable its efficient reuse through classification with established terminology. This paper contributes to data management aspects in Affective Computing and to automation support in emotion classification on the basis of a personal traits analysis. Hence, we describe the implementation of a taxonomy management system, derived from requirements of a case study that investigates the relationship between personality and emotions in Affective Computing. The study makes use of machine learning software developed by SenseCare, an EU-funded R&D project that applies Affective Computing to enhance and advance future healthcare processes and systems.

Media use cases for emergency services require mission-critical levels of reliability for the delivery of media-rich services, such as video streaming. With the upcoming deployment of the fifth generation (5G) networks, a wide variety of applications and services with heterogeneous performance requirements are expected to be supported, and any migration of mission-critical services to 5G networks presents significant challenges in the quality of service (QoS), for emergency service operators. This paper presents a novel SliceNet framework, based on advanced and customizable network slicing to address some of the highlighted challenges in migrating eHealth telemedicine services to 5G networks. An overview of the framework outlines the technical approaches in beyond the state-of-the-art network slicing. Subsequently, this paper emphasizes the design and prototyping of a media-centric eHealth use case, focusing on a set of innovative enablers toward achieving end-to-end QoS-aware network slicing capabilities, required by this demanding use case. Experimental results empirically validate the prototyped enablers and demonstrate the applicability of the proposed framework in such media-rich use cases.

Dementia has a severe impact on emotional functioning. People with dementia tend to find it difficult to recognize, articulate, and express their emotions. This can have a damaging effect on their mental health and the quality of their social relationships. With global populations increasingly aging, the need to address these issues becomes more prominent. One potential aid in tackling such problems is the use of sensor technologies and machine learning algorithms to make face-to-state analysis and classification of emotion status so as to provide care support. This paper describes the SenseCare system that uses affective computing methodology to capture, analyze, and store information on emotional outputs in the aim of providing effective tools for caregivers and medical professionals to provide more holistic care to people with dementia.

This paper describes a new emotional detection system based on a video feed in real-time. It demonstrates how a bespoke machine learning support vector machine (SVM) can be utilized to provide quick and reliable classification. Features used in the study are 68-point facial landmarks. In a lab setting, the application has been trained to detect six different emotions by monitoring changes in facial expressions. Its utility as a basis for evaluating the emotional condition of people in situations using video and machine learning is discussed.

This paper describes a new prototype system for detecting the demeanor of patients in emergency situations using the Intel RealSense camera system [1]. It describes how machine learning, a support vector machine (SVM) and the RealSense facial detection system can be used to track patient demeanour for pain monitoring. In a lab setting, the application has been trained to detect four different intensities of pain and provide demeanour information about the patient's eyes, mouth, and agitation state. Its utility as a basis for evaluating the condition of patients in situations using video, machine learning and 5G technology is discussed.

Multiple sclerosis (MS) is a progressive neurological disorder affecting between 2 and 2.5 million people globally. Tests of mobility form part of clinical assessments of MS. Quantitative assessment of mobility using inertial sensors has the potential to provide objective, longitudinal monitoring of disease progression in patients with MS.The mobility of 21 patients (aged 25-59 years, 8 M, 13 F), diagnosed with relapsing-remitting MS was assessed using the Timed up and Go (TUG) test, while patients wore shank-mounted inertial sensors.This exploratory, cross-sectional study aimed to examine the reliability of quantitative measures derived from inertial sensors during the TUG test, in patients with MS. Furthermore, we aimed to determine if disease status (as measured by the Multiple Sclerosis Impact Scale (MSIS-29) and the Expanded Disability Status Score (EDSS)) can be predicted by assessment using a TUG test and inertial sensors.Reliability analysis showed that 32 of 52 inertial sensors parameters obtained during the TUG showed excellent intrasession reliability, while 11 of 52 showed moderate reliability. Using the inertial sensors parameters, regression models of the EDSS and MSIS-29 scales were derived using the elastic net procedure. Using cross validation, an elastic net regularized regression model of MSIS yielded a mean square error (MSE) of 334.6 with 25 degrees of freedom (DoF). Similarly, an elastic net regularized regression model of EDSS yielded a cross-validated MSE of 1.5 with 6 DoF.Results suggest that inertial sensor parameters derived from MS patients while completing the TUG test are reliable and may have utility in assessing disease state as measured using EDSS and MSIS.

In most 3D work to date, people have looked at two situations: 1) a case in which power density is not a problem, and the parts of a processor and/or entire processors can be stacked atop each other, and 2) a case in which power density is limited, and storage is stacked atop processors. In this paper, we consider the case in which power density is a limitation, yet we stack processors atop processors. We also will discuss some of the physical limitations today that render many of the good ideas presented in other work impractical, and what would be required in the technology to make them feasible. In the high-performance regime, circuits are not designed to be “power efficient;” they're designed to be fast. In power-efficient design, the speed and power of a processor should be nearly proportional. In the high-performance regime, the frequency is (ever progressingly) sublinear in power. Thus, when the power density is constrained - as it is in high-performance machines, there may be opportunities to selectively exploit parallelism in workloads by running processor-on-processor systems at the same power, yet at much greater than half speed.

In this paper, we present a novel design methodology to combat the ever-aggravating high frequency power supply noise (di/dt) in modern microprocessors. Our methodology integrates microarchitectural profiling for noise-aware floorplanning, dynamic runtime noise control to prevent unsustainable noise emergencies, as well as decap allocation; all to produce a design for the average-case current consumption scenario. The dynamic controller contributes a microarchitectural technique to eliminate occurences of the worst-case noise scenario thus our method focuses on average-case noise behavior.

This paper presents the first multiobjective microarchitectural floorplanning algorithm for high-performance processors implemented in two-dimensional (2-D) and three-dimensional (3-D) ICs. The floorplanner takes a microarchitectural netlist and determines the dimension as well as the placement of the functional modules into single- or multiple-device layers while simultaneously achieving high performance and thermal reliability. The traditional design objectives such as area and wirelength are also considered. The 3-D floorplanning algorithm considers the following 3-D-specific issues: vertical overlap optimization and bonding-aware layer partitioning. The hybrid floorplanning approach combines linear programming and simulated annealing, which is shown to be very effective in obtaining high-quality solutions in a short runtime under multiobjective goals. This paper provides comprehensive experimental results on making tradeoffs among performance, thermal, area, and wirelength for both 2-D and 3-D ICs

Dedicated to my family, who have always put up with me. iii ACKNOWLEDGEMENTS I would like to express my sincere gratitude to Professor Sung Kyu Lim for his guidance of my research and his patience during my studies at Georgia Tech. I would like to thank my thesis committee members, their valuable suggestions. I would like to thank all the members of GTCAD and CREST groups for their support and friendship, especially, S. Ballapuram, and Mario Vittes who helped me in many ways throughout my years at Georgia Tech. My family has always supported me in all my decisions and for that I express my deepest gratitude and love. I also would like to thank my roommate and friend Christopher Tillotson who put up with me during many stressful times.

In this paper, we present the first multi-objective microarchitectural floorplanning algorithm for designing highperformance, high-reliability processors in the early design phase. Our floorplanner takes a microarchitectural netlist and determines the placement of the functional modules while simultaneously optimizing for performance and thermal reliability. The traditional design objectives such as area and wirelength are also considered. Our multi-objective hybrid floorplanning approach combining Linear Programming and Simulated Annealing is shown to be fast and effective in obtaining high-quality solutions. We evaluate the trade-off of performance, temperature, area, and wirelength and provide comprehensive experimental results.

Dataflow architectures provide an abundance of computing units that can be statically or dynamically configured to match the computing requirements of the given application. Wire delay has a reduced impact in dataflow architectures because only neighboring architectural entities are allowed to communicate within a single clock cycle. In this paper, the authors propose integer linear programming (ILP)-based placement and routing algorithms for mapping dataflow graphs (DFGs) to dataflow machines. The optimization process is guided by profiling information available from the compiler. The goal is to minimize the total execution time of the given application represented by a DFG under architectural constraints. A hierarchical method to handle the complexity of the initial ILP formulation is proposed. The profile-driven ILP algorithm reduces the total execution time of benchmark applications compared to the conventional wirelength-driven ILP approach. In addition, the ILP-based approach outperforms simulated annealing-based approach