For the first time, we demonstrate an error-free, 128Gbps (8x16Gbps) optical transceiver using a microring-based wavelength-division multiplexed (WDM) architecture. The optical transceiver ran for 12 hours with zero errors, resulting in a measured bit-error rate of <1.45e-15 per optical lane. The total number of bits sent during this time was ~691 terabits per lane and ~5.5 petabits aggregate across all lanes.

We demonstrate 128 Gbps/port (8-λ×16 Gbps/λ) natively error-free transmission across eight optical ports using a 8-port, 8-λ/port WDM remote laser source and a pair of monolithically integrated CMOS optical I/O chiplets with 4.96-5.56 pJ/bit optical Tx+Rx chiplet energy efficiency.

We demonstrate an electro-optic platform enabling a direct optical I/O interface in an ASIC package. The $5.5\mathrm{x}8.9\mathrm{mm}^{2}$ chiplet uses the Advanced Interface Bus (AIB), a parallel digital interface, to communicate to a host ASIC and integrates high-speed digital/analog circuits, optical modulators, photodetectors, and waveguides. Transmitters and receivers demonstrate data-rates up to 25Gbps at 4.9pJ/bit (Tx+Rx) and <10−12 BER error-free operation. We show a 32-channel, 512Gbps aggregate (across 4 Tx ports) wavelength-division multiplexed (WDM) transmit demonstration from a TeraPHY chiplet, running at 16Gbps per wavelength and 8 simultaneous wavelengths per port.

In this article, we present TeraPHY, a monolithic electronic-photonic chiplet technology for low power and low latency, multi-Tb/s chip-to-chip communications. Integration of the TeraPHY optical technology with open source advanced interconnect bus interface enables communication between chips at board, rack, and row level at the energy and latency cost of in-package interconnect. This enables the design of logically connected but physically separated large-scale and high-performance digital systems. The copackaging integration approach is demonstrated by integrating the TeraPHY die into the Intel Stratix10 FPGA multichip package.