A novel doping-based source/drain extension structure is introduced in three-dimensional fieldeffect transistors (3-D FETs), namely silicon-on-insulator (SOI) FinFETs and gate-all-around (GAA) FETs. Detailed TCAD simulation including the quantum mechanical effects demonstrates that compared to conventional devices with lightly doped drain (LDD) extensions of the same footprint, the proposed devices exhibit superior suppression of short-channel effects (SCEs), with higher on-state current (Ion), switching ratio (ION/IOFF), lower subthreshold swing (SS), and drain-induced barrier lowering (DIBL) achieved. In terms of intrinsic gain (Av), the proposed FinFET achieves a peak gain of 27.5 dB, significantly higher than the 22.2 dB of the LDD counterpart. The proposed GAAFET reaches a maximum value of 28.5 dB, compared to 19.8 dB for the LDD GAAFET. Such performance advantages demonstrate the potential of the proposed devices in both digital and analog circuit applications. Fabrication process to form the GAAFETs with the novel source/drain extensions is also discussed based on the bottom-up approach.

The degradation of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under high-frequency negative gate-pulsed stress was investigated. The results indicate that the degradation of a-IGZO TFTs shifts positively depending on the number of pulse repetitions rather than the accumulated stress time, which contrasts with the effects observed under low-frequency gate pulses. Notably, it is observed for the first time that the degree of degradation is determined by the pulse rising time (tr) and is independent of the pulse falling time (tf), a steeper pulse tr leads to more severe degradation. Based on degradation behaviors, we propose that the degradation mechanism under negative gate-pulse stress can be attributed to hot-carriers injection into the gate-oxide near the vicinity of source/drain electrodes and channel. Simulation-based quantitative analysis of transient lateral/vertical electric field and electron concentration at the vicinity verifies the proposed degradation model.

Amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) are widely used in flat-panel displays due to their high mobility and low-temperature fabrication. However, they are susceptible to threshold voltage shifts under negative-bias illumination stress (NBIS). This study compares the reliability of top-gate a-IGZO TFTs fabricated with different SiO2 gate insulator (GI) process conditions under NBIS. Results show that under low light intensity, degradation differences between devices made with the two process conditions are minimal. Under high light intensity and elevated temperature, top-gate a-IGZO TFTs with gate insulators prepared using a lower N2O ratio exhibit better NBIS stability, especially in short-channel devices.

Due to the bandgap limitation of amorphous InGaZnO4 (a-IGZO) and the lack of an effective light-trapping structure, the realization of broadband visible-light detection for a-IGZO thin film transistor (TFT) has become a challenge. In this work, a high-performance broadband absorber based on the Fabry-Pérot resonance and localized surface plasmon resonance was designed and fabricated. Based on the typical back-gate TFT structure, the absorber utilized the active layer a-IGZO and gate insulator Al2O3 as the middle dielectric layer and incorporated an Au/Cr nanostructure as the top metal layer. This structure exhibits an ultraviolet-visible broadband absorption property with an average visible absorptivity of 82%. Then we integrated the broadband absorber structure into the a-IGZO TFT to achieve an all-in-one integration structure, which successfully enhanced its optoelectronic performance and extended its photoresponse to 600 nm. The optimized specific detectivity values of the integrated TFT for ultraviolet, blue light, green light, and orange light were 2.55×1011, 4.96×1010, 6.45×109, and 2.08×107 Jones, respectively, exceeding those of the conventional TFT structure by more than 16 times. The integrated a-IGZO TFT is manufactured by a relatively reliable fabrication process which is compatible with standard TFT fabrication processes, thereby demonstrating reproducible photodetection performance in large-area production.

The instability phenomenon under negative bias illumination stress (NBIS) remains a major challenge for the application of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) in active-matrix displays. In this paper, we employ fluorine plasma treatment and a segmented metal cover line approach to enhance the stability of elevated metal metal-oxide (EMMO) a-IGZO TFTs under NBIS. At room temperature, after 15 minutes of fluorine treatment, Delta VON decreases from 5.53 V to 2.02 V. This improvement is mainly attributed to the fact that fluorine atoms fill the ionized oxygen vacancies in a-IGZO, thereby reducing the density of defect states in the channel. Further adding 2.0 mu m wide metal-covered wires reduces the Delta VON to 0.35 V. Under 80 degrees C NBIS, the Delta VON is limited to 3.79 V. This improvement is mainly attributed to the light-shielding effect of the metal lines and the passivation of oxygen vacancies by fluorine, thereby enhancing device stability under NBIS.

The mechanisms for the degradation of amorphous indium-gallium-zinc oxide thin-film transistors under positive gate bias stress (PBS) and the degradation mitigation under simultaneous DC gate and drain biases stress are clarified. The observed reduction in the threshold voltage (Vth) during PBS is ascribed to the ionization of oxygen vacancies, which is promoted by electron accumulation under the vertical electric field. The introduction of a drain bias can reduce the vertical electric field near the drain and mitigate the degradation caused by the gate. The recovery-like behavior under simultaneous DC gate and pulsed drain bias reveals that the flow of electrons in the channel under DC gate and drain biases also accelerate the neutralization of ionized oxygen vacancies and thus the degradation near the source.

In this study, we propose a methodology to extract the carrier impact ionization rates ( $\alpha $ ) of poly-Si films with different crystallinity based on TCAD simulation of thin-film transistors (TFTs). The dependence of $\alpha $ on the total trap density was also investigated. First, the TCAD simulation model of TFTs was calibrated by precisely fitting the measured transfer and output characteristic curves of poly-Si TFTs, and the trap density of states (DOSs) in such poly-Si films was determined. Subsequently, by including the impact ionization model in TCAD simulation, $\alpha $ was successfully extracted by precisely fitting the kink current observed in the output characteristics. It is shown that $\alpha $ of poly-Si films strongly depends on their crystallinity, and the preexponential factor significantly increases with the trap density following a power-law dependency with an exponent of ~3.2. This work presents, for the first time, a quantitative analysis of $\alpha $ for poly-Si films of different crystallinity, and explicitly gives the dependency of $\alpha $ on the trap density of poly-Si films.

Negative bias illumination stress (NBIS) instability is an important issue to overcome for the application of amorphous InGaZnO4 (a-IGZO) thin-film transistors (TFTs) in flat-panel displays. In this work, TFTs based on praseodymium (Pr)-doped a-IGZO were fabricated, and their NBIS stability at different temperatures was characterized. The transfer curve shifts in the negative gate bias direction under NBIS, and the magnitude of the shift increases significantly at elevated temperatures even with a weak illumination intensity. Benefiting from Pr doping, the oxygen vacancies in the channel a-IGZO can be reduced for TFTs with a metal cover layer after annealing in an oxygen atmosphere. Thus, significantly improved NBIS stability of a-IGZO TFTs at both room temperature and elevated temperatures is demonstrated.

After applying combined DC gate voltage and drain voltage stress to interdigital-structured a-IGZO TFTs with different numbers of channels, their transfer characteristic curves exhibit varying degrees of positive shift. A greater number of channels results in a larger threshold voltage shift. Additionally, the transfer curve of the TFT with a channel width of 1000 μm exhibits a hump phenomenon. The degradation of interdigital-structured a-IGZO TFTs under DC gate and drain voltage stress originates from the self-heating effect. Since the multiple channels of the interdigital-structured TFT are formed within the same a-IGZO active island, the heat generated in each channel cannot be dissipated laterally quickly into the ambient atmosphere. Consequently, Joule heat accumulates within the a-IGZO active island, leading to varied degradation across channels at different positions.

Short‐channel elevated‐metal metal‐oxide (EMMO) TFTs exhibit significantly worse stability after post‐annealing in nitrogen atmosphere compared to long‐channel devices. This short‐channel effect (SCE) was attributed to the oxygen vacancy defects, which is verified by TCAD simulation.

Negative bias illumination stress (NBIS) instability presents a significant challenge for the application of amorphous InGaZnO4 (a-IGZO) thin-film transistors (TFTs) in active-matrix displays. In this article, we demonstrate the effectiveness of incorporating split metal lines to enhance the NBIS stability with elevated-metal metal-oxide (EMMO) a-IGZO TFTs. The negative shift in subthreshold current after NBIS is successfully reduced from 3.92 V to 0.54 V when the width of the metal line reaches 2.0 mu m, which is now predominantly caused by negative gate bias induced redistribution of pre-existing ionized oxygen vacancies in the channel a-IGZO. The enhanced NBIS stability is achieved through the illumination shielding effect by the metal lines and passivation of oxygen vacancies under the metal lines by oxygen laterally diffused from the spacing regions between the metal lines. The less degraded a-IGZO regions under the metal lines determined the overall performance of the a-IGZO TFT after NBIS.

This chapter provides an in-depth analysis of the reliability issues associated with thin-film transistors (TFTs), focusing on the common defects found in silicon-based and metal-oxide TFTs. It discusses the various types of defect states and the typical degradation mechanisms that impact the performance of TFTs. The chapter emphasizes the need for comprehensive understanding and strategies to mitigate these reliability challenges in TFT applications.

The reliability of flexible p-type low temperature poly-silicon thin film transistors (TFTs) under sole illumination stress was investigated. As the TFT was exposed to illumination, the transfer characteristic curves of the TFTs shifted positively, accompanied by an increase in the off-state current. Through altering the wavelength and intensity of the light, the degradation mechanism for TFTs under illumination stresses can be attributed to photoexcited carriers and residual hydrogen diffusion from the Si3N4 layer to air, leading to a forward shift in the threshold voltage. Moreover, TFTs exposed to the air for an extended period can also effectively remove residual hydrogen in the silicon nitride layer, thereby effectively suppressing photoinduced degradation of the device and improving its reliability.

This study investigates the source-drain metal line microcrack propagation and failure behavior of flexible lowtemperature poly-Si thin-film transistors (LTPS TFTs) under dynamic stretch stress. It is observed for the first time that the microcrack growth and failure of the device under dynamic stretch are correlated with ambient conditions. Ambient $\mathrm{H}_{2} \mathrm{O}$ and $\mathbf{O}_{2}$ influence microcrack propagation and failure of the device under dynamic stretch, where $\mathrm{H}_{2} \mathrm{O}$ is the key factor leading to mechanical reliability decline, while $\mathrm{O}_{2}$ requires $\mathrm{H}_{2} \mathrm{O}$ to take effect. Clarifying the ambient-dependent microcrack growth and failure behavior of the device under dynamic stretch is of great significance for ensuring the mechanical reliability of TFTs.

The degradation of p-type poly-Si TFTs under various dynamic gate pulse stresses was investigated. We clarify the impacts of pulse rising time (t(r)) and pulse falling time (t(f)) on device degradation, respectively. Under dynamic PBTI stress or dynamic gate voltage stresses swinging between the on-state and off-state, both the electrons trapping into gate oxide and the traps generation near the source/drain are responsible for the two-stage degradation, which can be explained by the hot carrier (HC) effect using the nonequilibrium pn junction degradation model. To suppress the dynamic degradation, a new four-terminal TFT is designed with a carrier injection structure. A relieved degradation with an additional hump phenomenon can be observed for the first time under the same pulsed gate stress since the channel state can follow the pulse transition, eliminating the HC effect. More electrons trapping at the channel side is proposed to explain the hump phenomenon and is proven by the TCAD simulation.

This article investigates the effects of different kinds of trap states on the degradation of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under alternating current (ac) gate pulse bias stress. P-type TFTs with different ON-state and subthreshold characteristics are fabricated, and thus, different distributions of donor-like tail states and deep states are achieved. The decrease of ON-state current is the dominant degradation phenomena for all the TFTs due to trap state generation occurring during the pulse rising edges. TFTs with higher donor-like trap states show severe degradation. It is attributed to the higher transient lateral electric field and hole concentration due to the higher donor-like deep state density, while acceptor-like trap states do not contribute to the degradation of p-type poly-Si TFTs under ac gate bias stress.

A recently proposed ultrathin body and buried oxide (UTBB) SOl MOSFETs with non-LDD source/drain extensions, which are induced by embedded fixed charges within the BOX, is investigated for analog circuit applications. TCAD simulation shows that the proposed device exhibits superior characteristics in suppressing short-channel effects while concurrently achieving higher transconductance $(g_{\mathfrak{m}})$ , lower output conductance $(g_{\mathrm{d}\mathrm{s}})$ and higher intrinsic gain $(A_{\mathrm{v}})$ , as well as reduced kink current. In the proposed device, onset of the kink current effect occurs at a larger $Vo\mathrm{s}$ bias compared to the LDD device, besides, it has a weaker drain-induced barrier lowering effect. Both factors lead to a flat VDS region available in the output curve above the drain saturation voltage with lower $g_{\mathrm{d}\mathrm{s}}$ obtained.

An ultrathin body and buried oxide (UTBB) SOI MOSFETs with novel non-LDD source/drain extensions are proposed, where highly conductive paths are induced by positive charges locally distributed in the buried oxide (BOX) connecting the channel and respective source and drain. TCAD simulation shows that the performance of the proposed MOSFET is superior to conventional UTBB MOSFETs of the same footprint in terms of drain-induced barrier lowering (DIBL), subthreshold swing (SS), and off-state current. Even with much relaxed device dimensions, such as thicker silicon body and/or BOX either with or without introducing a ground plane (GP), it can still achieve higher driving current and similar short-channel effect (SCE) immunity as the conventional UTBB MOSFETs. Such advantages of the proposed MOSFETs are due to better gate electrostatics over the channel benefited from the novel source/drain extensions.

The dynamic R-ON degradation in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) with different passivation layers(Si(3)N(4 )or Si3N4/ZrO2 stack) under off-, semi-on, and ON-state stress have been investigated in this work. Under the OFF-state stress of 40 V, a 20% reduction in the maximum drain current has been observed in devices passivated withSi3N4, along with a degraded R-ON that is 1.42 times higherthan the initial R-ON. In contrast, devices passivated with Si3N4/ZrO2 stack have only shown a 2% reduction, and theRONdegradation is only 1.03 times higher than the initial R-ON. This can be attributed to the different interface statespresent in the two devices. According to the multifrequencyC-Vcurves, the Si3N4/GaN-cap interface trap density is inthe range of 2x10(13)-5.5x10(13 )from EC-0.47 to EC-0.37 eV, and ZrO2/GaN-cap interface trap density is in therange of 2.7x10(12)-1.2x10(13 )from EC-0.47 to EC-0.31 eV.Under the semi-on state stress, the dynamic R-ON degra-dation exhibits a "bell-shaped" behavior in the Si3N4/ZrO(2 )stack passivated sample. Arrenhi us plots indicate that the sample passivated by Si3N4has an activation energy of 0.06 eV, while the sample passivated by Si3N4/ZrO2 stack has an activation energy of 0.16 eV, which means adeeper trap distribution. The R-ON degradation under semi-on/ON-state stress in Si3N4/ZrO2 passivated devices can beattributed to the hot-electron-related injection mechanism.Device designers must consider the trade-off between the high breakdown voltage (BV) and the R-ON degradation in Si3N4/ZrO2 passivated devices.