Spin-orbit electronics (spin-orbitronics) has been widely discussed for enabling nonvolatile devices that store and process information with low power consumption. The potential of spin-orbitronics for memory and logic applications has been demonstrated by perpendicular anisotropy magnetic devices comprised of heavy-metal/ferromagnet or topological-insulator/ferromagnet bilayers, where the heavy metal or topological insulator provides an efficient source of spin current for manipulating information encoded in the bistable magnetization state of the ferromagnet. However, to reliably switch at room temperature, spin-orbit devices should be large to reduce thermal fluctuations, thereby compromising scalability, which in turn drastically increases power dissipation and degrades performance. Here, we show that the scalability is not a fundamental limitation in spin-orbitronics, and by investigating the interactions between the geometry of the ferromagnetic layer and components of the spin-orbit torque, we derive design rules that lead to deeply scalable spin-orbit devices. Furthermore, employing experimentally verified models, we propose deeply scaled spin-orbit devices exhibiting high-speed deterministic switching at room temperature. The proposed design principles are essential for design and implementation of very-large-scale-integration (VLSI) systems that provide high performance operation with low power consumption.

Previous works established the capacity region for some special cases of discrete memoryless degraded cognitive interference channel (CIC) with unidirectional destination cooperation (UDC). In this letter, we characterize the capacity region of the general discrete memoryless degraded CIC-UDC. The obtained results imply that the capacity region is achieved by the Gel'fand-Pinsker coding at the cognitive transmitter, superposition coding at the primary transmitter and decode-and-forward at the relay. Furthermore, using this general result and a novel converse analysis, we establish the capacity of the Gaussian degraded CIC-UDC, which had been open until this work.

High density embedded memories have been demanded increasingly to enhance the performance and reduce the power dissipation of advanced systems, such as multicore processors, which have been used in a wide variety of applications from servers to Internet-of-things (IoT) devices. In this paper, a memory cell, referred to as the gain-cell magnetoresistive random access memory (gMRAM), is introduced. The gMRAM significantly reduces the cell area per bit as compared to state-of-the-art embedded memories, provides opportunities for the joint enhancement of performance and reduction of power dissipation, and provides a natural basis for in-situ computing. A gMRAM cell simultaneously retains two bits, a nonvolatile bit using a magnetic tunnel junction (MTJ) and a dynamic bit using the access transistor of the MTJ. The two bits are independently and nondestructively accessible for read and write. This paper focuses on the design and characterization of the gMRAM cell, array architecture, and read/write circuitry. Simulation results from an 8 kb gMRAM array using a 14 nm standard FinFET CMOS technology demonstrate a 750 ps / 475 ps access time for dynamic read/write, while the nonvolatile bit can be read from or written to the same cell with a, respectively, 750 ps and 3.5 ns access time. The gMRAM cell area per bit is 3× (2×) smaller than a SRAM (3T eDRAM) cell in the same technology.

The spin degree of freedom in magnetic devices has been discussed widely for computing, since it could significantly reduce energy dissipation, might enable beyond Von Neumann computing, and could have applications in quantum computing. For spin-based computing to become widespread, however, energy efficient logic gates comprising as few devices as possible are required. Considerable recent progress has been reported in this area. However, proposals for spin-based logic either require ancillary charge-based devices and circuits in each individual gate or adopt principals underlying charge-based computing by employing ancillary spin-based devices, which largely negates possible advantages. Here, we show that spin-orbit materials possess an intrinsic basis for the execution of logic operations. We present a spin-orbit logic gate that performs a universal logic operation utilizing the minimum possible number of devices, that is, the essential devices required for representing the logic operands. Also, whereas the previous proposals for spin-based logic require extra devices in each individual gate to provide reconfigurability, the proposed gate is ‘electrically’ reconfigurable at run-time simply by setting the amplitude of the clock pulse applied to the gate. We demonstrate, analytically and numerically with experimentally benchmarked models, that the gate performs logic operations and simultaneously stores the result, realizing the ‘stateful’ spin-based logic scalable to ultralow energy dissipation.

Devices with ferromagnetic layers possessing a perpendicular magnetic easy axis are of great interest due to miniaturization capability and thermal stability, retaining deeply scaled magnetic bits over long periods of time. While the tunneling magnetoresistance effect has significantly enhanced electrical reading of magnetic bits, fast and energy efficient writing of magnetic bits remains a challenge. Current-induced spin-orbit torques (SOTs) have been widely considered due to significant potential for fast and energy-efficient writing of magnetic bits. However, to deterministically switch the magnetization of a perpendicularly magnetized device using SOTs, the presence of a magnetic field is required, which offsets possible advantages and hampers applications. In this paper, a perpendicularly magnetized device is presented, which, without the need for a magnetic field, can be deterministically switched in both toggle and nontoggle modes using a damping-like SOT induced by an in-plane current pulse. This capability is realized by shaping the magnetic energy landscape. Present device does not require any materials other than those widely utilized in conventional spin-orbit devices. The device provides two orders of magnitude enhancement in switching energy-time product as compared with state-of-the-art perpendicularly magnetized devices operating on spin-transfer torques.

Electrical control of a magnetic tunnel junction (MTJ) through spin-orbit torques (SOTs) offers opportunities to introduce MTJs into high-performance, low energy applications. SOTs support a high-speed and energy-efficient three terminal MTJ with perpendicular-to-the-plane magnetization (PMTJ). The read path is separated from the write path, enhancing the reliability of the device. SOTs exhibit two coexisting contributions: 1) a damping-like torque and 2) a field-like torque. In this paper, a physics-based compact model for a three terminal PMTJ is presented, which accurately models the magnetic, electrical, and thermal behaviors of a PMTJ controlled through SOTs. The proposed compact model is validated with experimental data, exhibiting reasonable accuracy with an average error of <;5.4%. The integration capability of the proposed compact model with CMOS technology is also demonstrated.

A nonvolatile flip-flop (NVFF) is proposed, where magnetic tunnel junctions (MTJs) are incorporated into a CMOS flip-flop (FF) to enable nonvolatility. The voltage-controlled magnetic anisotropy (VCMA) effect is utilized to back up the latched data into MTJs before the power supply is turned off. Switching an MTJ through the VCMA effect does not require a dedicated write circuit for data backup, resulting in reduced area as compared with NVFFs exploiting the spin transfer torque (STT) switching mechanism. In a VCMA-based NVFF, the MTJs are coherently switched, enabling ultra-energy efficient data backup with subnanosecond backup time. Simulation results exhibit more than a 342× (33.7×) improvement in data backup energy per bit, and more than 35.5× (7.7×) improvement in data backup delay per bit as compared with the most efficient STT-based NVFFs (spin Hall effect-based NVFF). The energy efficiency of the VCMA-based NVFF results in sufficiently short breakeven times, enabling effective fine-grain power gating.

Electrical control of magnetic tunnel junctions (MTJs) provides opportunities to introduce MTJs into high-performance applications requiring low power consumption. The magnetic state of an MTJ can be electrically controlled through: 1) the spin transfer torque (STT) effect; 2) the voltage controlled magnetic anisotropy (VCMA) effect; and 3) the fusion of STT and VCMA. Several compact models have been published for MTJs. All of these models consider an MTJ whose magnetic state is controlled through the STT effect. In this paper, a model of an MTJ comprising a free layer, an analysis layer, and a spin polarizing layer is described. The MTJ compact model, adaptive compact MTJ (ACM) model, includes the effects of asymmetry on the MTJ behavior, and models a device controlled through the STT, VCMA, or a fused STT-VCMA mechanism. The ACM model includes the dynamics of the junction temperature. The proposed model can be adapted to experimental configurations including in-plane MTJ (IMTJ), IMTJ with a perpendicular-to-the-plane polarizer, perpendicular-to-the-plane MTJ (PMTJ), and PMTJ with an additional easy axis. The ACM model is validated with published experimental data, showing reasonably accurate results with an average error of less than 6%.

The primary way of providing real-time speech to text captioning for hard of hearing people is to employ expensive professional stenographers who can type as fast as natural speaking rates. Recent work has shown that a feasible alternative is to combine the partial captions of ordinary typists, each of whom is able to type only part of what they hear. In this paper, we extend the state of the art fixed-window alignment algorithm (Naim et al., 2013) for combining the individual captions into a final output sequence. Our method performs alignment on a sliding window of the input sequences, drastically reducing both the number of errors and the latency of the system to the end user over the previously published approaches.

In this paper, we investigate the problem of communication over cognitive interference channel (CIC) with partially cooperating (PC) destinations (CIC-PC). This channel consists of two source nodes communicating two independent messages to their corresponding destination nodes. One of the sources, referred to as the cognitive source, has a noncausal knowledge of the message of the other source, referred to as the primary source. Each destination is assumed to decode only its intended message. In addition, the destination corresponding to the cognitive source assists the other destination by transmitting cooperative information through a relay link. We derive a new upper bound on the capacity region of discrete memoryless CI-CPC. Moreover, we characterize the capacity region for two new classes of this channel: (1) degraded CIC-PC, and (2) a class of semideterministic CIC-PC.

We derive the capacity region of two classes of the discrete memoryless state-dependent cognitive interference channels (SD-CICs) with noncausal channel state information known to only the cognitive transmitter: semideterministic SD-CIC and deterministic SD-CIC. We also provide new inner and outer bounds on the capacity region of the general SD-CIC. We prove that the new outer bound is the capacity region of the SD-CIC in the better cognitive decoding regime when both the cognitive transmitter and its corresponding receiver are aware of the channel state information in a noncausal manner.

We derive a new upper bound on the capacity region of the discrete memoryless partially cooperative relay cognitive interference channel (PC-RCIC). We show that our new upper bound is the capacity region of the semideterministic discrete memoryless PC-RCIC, where the channel output observed by the relay is a deterministic function of the channel inputs.

We consider a fading Gaussian cognitive relay multiple-access channel (CR-MAC), consisting of K sources and an active cognitive relay that wish to simultaneously communicate with a single destination. We assume that the relay has its own message to communicate and is aware of the messages of the other K sources non-causally. Furthermore, the message of the relay and the messages of the other K sources are independent. Assuming that all the sources, the cognitive relay and the destination are aware of the instantaneous channel state information (CSI) we characterize the ergodic capacity region. For the case where the cognitive relay does not have its own message to transmit, we derive the optimal power allocation strategies that achieve any arbitrary point on the boundary surface of the capacity region.

The cooperative relay cognitive interference channel (RCIC) is a four-node network with two source nodes (primary source and cognitive source) and two destination nodes, in which sources try to communicate at certain rates with their corresponding destinations simultaneously through a common medium and each destination can act as a relay to assist the other one. In this paper, we study partially and fully cooperative state-dependent relay cognitive interference channels (RCICs) with perfect causal channel state information (CSI). For each of these channels, we investigate three different cases. For the first case, perfect causal CSI is available at both the source and relay nodes; for the second case, perfect causal CSI is only known to the relay nodes; and for the third case, perfect causal CSI is only available at the cognitive source. We obtain the capacity region of each case, for a degraded version of the channel. Our results include the previously obtained results for the degraded relay, broadcast and relay broadcast channels with perfect causal CSI, as special cases.

The cooperative relay cognitive interference channel (RCIC) is a four-node network with two source nodes (primary source and cognitive source) and two destination nodes, in which sources try to communicate at certain rates with their corresponding destinations simultaneously through a common medium and each destination can act as a relay to assist the other one. For the partially cooperative RCIC (PC-RCIC), in which only one of the destinations (corresponding to the cognitive source) acts as a relay, we derive an achievable rate region based on using rate splitting and superposition coding at the cognitive source, and using decode-and-forward scheme at the relay. For the degraded PC-RCIC, we characterize the capacity region. We also investigate the Gaussian PC-RCIC in details. In this case, we present the achievability and converse arguments for a class of degraded Gaussian PC-RCIC and determine the capacity region of this class. Obtained results offer the cooperative relaying as an effective strategy for improving the capacity region of the cognitive interference channels (CICs).