In this article, a doped fully depleted silicon on insulator (FDSOI) behavior for the 65-nm partially depleted silicon on insulator (PDSOI) technology is demonstrated to understand the output voltage shift of a voltage reference (VR) undergoing dose deposition in real time. From an in-depth top-bottom analysis, including both experiments and technology computer aided design (TCAD)/simulation program with integrated circuit emphasis (SPICE) simulations, we highlighted this unexpected doped FDSOI behavior. This study shows how it worsens the total ionizing dose (TID) effects due to the coupling effect between the front and back interfaces, not usual in this technology. A new threshold voltage model considering channel doping and TID is developed, showing how doping concentration is an important hardening parameter. This model is reused, in a multiscale approach, to reproduce the output voltage shift of a VR based on the PDSOI transistor degradation.

In this work, we developed a simulation methodology with the Synopsys Sentaurus Technology Computer Aided Design (TCAD) suite in order to analyze Total Ionizing Dose (TID) effects in 65 nm Body Contacted (BC) Partially Depleted (PD) SOI technology for a MOS transistor including a hump characteristic induced by an unknown parasitic transistor.

In this article, a heavy ion-induced single-event transient (SET) compact model is presented for the body-contacted partially depleted silicon on insulator (BC PDSOI) MOS transistor, which is interfaced with our Geant4 particle-matter interaction code. Cross comparisons with technology computer aided design (TCAD) simulations are provided as well as some modeling adds-on to existing models, addressing the case of energy deposition in the source and drain and improving the body discharge description through the body contact. In previous works, the experimental calibration of existing compact models rarely relies on the transistor-level collected charge distribution, measured during a heavy ions irradiation run. Still, the collected charge is a key measurable quantity as its value strongly influences circuit-level effects (like single-event upset (SEU) in memories). Moreover, reproducing the collected charge distribution within an irradiation run-through simulation is providing a proof that the stochastic nature of the experiment is correctly captured by the SET compact model. In this work, we expose an experimental statistical calibration procedure based on collected charge data obtained in Grand Accelerateur National d'Ions Lourds (GANIL).

A charge build-up model implemented in a netlist coupled with L-UTSOI model, which takes into account the deposited dose as an input parameter, is presented for Fully Depleted Silicon On Insulator (FDSOI) transistors. The model is based on the rate equations governing the physical processes of the charge build-up in the oxides. Based on in-house irradiation measurement, our model is calibrated on experimental Id-Vg characteristics in order to find the model parameters and extract the contribution of the oxide and interface trapped charges.

SET compact modeling for SEU prediction is faced to new challenges for advanced technological nodes. Some works have already addressed these challenges, proposing modeling approach for new relevant physical aspects like bipolar amplification, 3D charge deposit morphology, and bipolar amplification. Very recently, we have developed a fully compact SET model for very integrated technologies taking these effects into account, suitable for SPICE simulations. In this paper, we propose to couple this SET compact model with MUSCA SEP3 soft errors simulation plateform, in order to address soft error risk assessment for very integrated technologies. SBU/MCU predictions are performed in FDSOI based SRAM memories after TCAD calibration of our SET compact model. The purpose is to show how bipolar amplification, 3D charge deposit morphology, and SET/circuit coupling are able to influence simulated SBU/MCU cross sections values.

The total ionizing dose (TID) sensitivity of mature and innovative technologies is investigated using both ionizing radiation experiments and Monte-Carlo simulations to discuss the potential of spectral photon radiation sources as an alternative for radiation effects studies. The impact of both technological and radiation test parameters on effective TID deposition is also discussed. All the layers struck by the incident radiation flux before reaching the targeted sensitive oxide are the major contributors of final ionizing dose deposits, rather than the actual sensitive oxide itself.

Total ionizing dose (TID) effects induced by different photon sources are studied in MOS devices. The dose factor (DF), defined as the ratio between dose deposition in dosimeter and actual dose deposition in MOS-sensitive oxides (SOs), is estimated using Monte-Carlo simulations of energetic photons striking simple device structures. An effective TID approach is proposed to account for both the real ionizing dose depositions in small volumes and the charge yield. This method is applied to a silicon-on-insulator (SOI) technology using three photon sources: the usual ARACOR and 60Co sources, which deliver several tens of kiloelectron volt photons and ~1.25-MeV photons, respectively, and a third facility named ORIATRON, a 6-MeV electron linear accelerator that produces photons on a wide energy spectrum. This topic, investigated intensively in the literature a few decades ago, is revisited in the context of several evolutions including: new radiation sources, novel simulation tools, and device scaling, which all impact ionizing dose deposition in microsensitive volumes of current electronic technologies. Dedicated numerical simulations demonstrate the importance of taking into account the entire stack of materials in order to get the most accurate estimations of TID in the SO. Descriptions of the back-end-of-line (BEOL) layers (especially when the technology uses copper), the polysilicon gate, the Buried OXide (BOX) (for SOI devices), but also of the substrate and package are mandatory in these simulations, since dose enhancement and/or backscattered photons can be a significant source of TID variation in the gate oxide. Also the package lid composition and its thickness can be major TID contributors. The results show that the use of a prefilter with lead and aluminum can optimize ionizing dose deposition

Transient Ionizing Radiation Response (TIRR) of Metal Oxide Semi-Conductor Field Effect Transistors (MOSFET) is a transient parasitic current induced by ionizing radiations. These radiations might have various both spatial and temporal profiles depending on the considered application. In recent work, we have developed Single Event Transient (SET) compact model for MOSFET, which is the parasitic current pulse induced by an individual ionizing particle. This model has been implemented in Verilog-A, as an equivalent electrical circuit made of many RC circuits. In this work, we extend this model to any kind of TIRR of SOI MOSFET, keeping the same compact modeling approach. Cross-comparisons with realistic 3D TCAD simulations of SOI MOSFET are then made.

Single Event Transients (SET) are ionizing particles induced current pulses which are able to generate soft errors in CMOS circuits. In Silicon-on-Insulator (SOI) technologies, bipolar amplification phenomena is more significant due to presence of the Burried Oxide (BOX), which is detrimental to soft errors sensitivity. State of the art FDSOI SET models account for bipolar amplification through a dynamic pre-factor. This approach is mainly empirical and not compact. In this work, we propose a SET compact model for FDSOI MOSFETs including a physical modeling of bipolar amplification. Results are validated through TCAD simulations. A circuit level approach is proposed considering arbitrary generation within functional SRAM cell. This approach allows more realistic Single Event Upset (SEU) prediction and we show how circuit level generation can influence SEU prediction.

The total ionizing dose (TID) is a well-known reliability issue for integrated circuits (ICs). It consists in changes of MOSFETs dc characteristics following the irradiation of devices in a given radiative environment, such as space environment. TID effects have been investigated from an experimental and theoretical standpoint, and the compact modeling of TID effects has been included into BULK tr...

Single Event Transients (SET) are important issues concerning reliability of CMOS circuits. They lead to occurrence of soft errors in integrated circuits, such as Single Event Upset (SEU) which consists in unexpected bit state switch in SRAM cells [1], [2]. We can find models which describe SET in literature [1], [5] but they are not compact (i e. physical model implemented in Verilog-A). In previous work [6], we proposed a theoretical SET model but the implementation in Verilog-A was still challenging. Here, we describe the implementation in Verilog-A of this model and use it through standard SPICE simulations to study the effect of SET on SRAM cell and shift register.

Single Event Transient (SET) is an important issue concerning reliability of MOS devices. Lots of experimental and simulation works have already been done [1- 4] but few of them are dealing with compact modelling. In this paper, we develop a physical model which describes the transient current pulse which appears at the electrodes of a Bulk MOSFET after the striking of an ionizing particle in the device. The validation of the model has been done by some confrontations with TCAD simulations. It turned out that the developed model has an innovative aspect for implementation into SPICE simulator.