Silicon holds significant potential as a material for future quantum processors. Transistors built in silicon-on-insulator technology and functioning as silicon qubit devices can be fabricated using industry-standard processes, allowing for easy integration with classical control hardware. However, achieving precise management of carrier transfer within the transistor channel is essential, requiring the elimination of electrically active defects that could act as recombination centers. Optimizing such a device demands a detailed characterization of the channel to assess the material purity. This study examines the presence of defects in the channel of fully depleted silicon-on-insulator transistors designed for qubit applications. Source and drain electrodes were connected together and voltage pulses were applied to the gate contact to perform capacitance deep level transient spectroscopy (DLTS) measurements. Electrical simulations conducted using Sentaurus device simulator were used to figure out the extension of the depleted region in the channel. By adjusting the gate voltages, we were able to probe the channel and localize the electrically active defects responsible for DLTS signals. Three dominant hole traps were detected at, respectively, 0.54, 0.57, and 0.65 eV above the valence band edge in the source/drain regions and were associated with bulk and Si/SiO2 interface defects. Their origin is likely related to the damage produced during the formation of p-doping by implantation. This study highlights not only the high quality of the channel material below the gate stack but also the need to keep the source and drain regions far from the gate edges to improve the qubit stability.

This work proposes a Verilog-A SPICE model for Ferroelectric Random Access Memories (FeRAM) device to manage major loops hysteresis including different ferroelectric distributions of Preisach-like approach. Our model is validated on different circuit simulators in different configurations such as 16kbit 1T-1C FeRAM array to demonstrate the model's capability in terms of robustness.

The modeling of FD-SOI transistors is a challenging task because it requires to deal with two potential conduction channels that are more or less coupled together. L-UTSOI has been developed to fulfill this need. It incorporates all the physical effects required to describe the behavior of aggressively scaled transistors and, through the years, it has been extended to high frequency operations and cryogenic temperatures to enable a wider use of FD-SOI technologies.

In this article, a doped fully depleted silicon on insulator (FDSOI) behavior for the 65-nm partially depleted silicon on insulator (PDSOI) technology is demonstrated to understand the output voltage shift of a voltage reference (VR) undergoing dose deposition in real time. From an in-depth top-bottom analysis, including both experiments and technology computer aided design (TCAD)/simulation program with integrated circuit emphasis (SPICE) simulations, we highlighted this unexpected doped FDSOI behavior. This study shows how it worsens the total ionizing dose (TID) effects due to the coupling effect between the front and back interfaces, not usual in this technology. A new threshold voltage model considering channel doping and TID is developed, showing how doping concentration is an important hardening parameter. This model is reused, in a multiscale approach, to reproduce the output voltage shift of a VR based on the PDSOI transistor degradation.

In this paper, we explore the effect of mechanical stress on the electrical parameters, for the first time at cryogenic temperatures, using L-UTSOI 102.7 compact model. We update the model to ensure robustness and precision down to cryogenic temperatures and then we benchmark it with industrial 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFET) both at 300K and 4.2K. We observe the stress evolution with temperature through the extracted parameters of our model, which acts as a reference for the numerical mechanical simulations. The simulation provides with meaningful insights on device performance.

This paper provides an improved surface potential equation for compact modeling of dynamically depleted silicon-on-insulator MOS device. It removes the non-physical front-gate capacitance prediction and the discontinuity at the flat-band condition present in previous works. It also includes for the first time the back gate effect observed at negative back gate voltage when the silicon film is partially depleted. It relies on, firstly, an approximated description of the front-depletion/back-accumulation mode of operation that has always been ignored by now, and secondly, an appropriate mathematical conditioning. The model is validated by 3D TCAD simulations.

This paper presents an analytical expression for the FDSOI MOSFETs subthreshold slope model accounting for low electric field quantum mechanical effect. The expression is derived from the perturbation theory applied to the system Hamiltonian considering the inversion layer carriers as particles in a one-dimensional box with an applied electric field the Hamiltonian. The effect is implemented by the introduction of a correction factor Γ 0 into the classical subthreshold slope analytical expression. Γ 0 is a function of the silicon film thickness square times temperature product and depends on the effective masses. The model is validated by its comparison with self-consistent one-dimensional Poisson-Schrödinger simulations and demonstrates unprecedented accuracy, in all studied temperature and bias range. Implemented into the inversion charge model, the correction describes better the back biasing dependence of the FDSOI MOSFET experimental subthreshold drain current.

Spins in semiconductor quantum dots constitute a promising platform for scalable quantum information processing. Coupling them strongly to the photonic modes of superconducting microwave resonators would enable fast non-demolition readout and long-range, on-chip connectivity, well beyond nearest-neighbor quantum interactions. Here we demonstrate strong coupling between a microwave photon in a superconducting resonator and a hole spin in a silicon-based double quantum dot issued from a foundry-compatible MOS fabrication process. By leveraging the strong spin-orbit interaction intrinsically present in the valence band of silicon, we achieve a spin-photon coupling rate as high as 330~MHz largely exceeding the combined spin-photon decoherence rate. This result, together with the recently demonstrated long coherence of hole spins in silicon, opens a new realistic pathway to the development of circuit quantum electrodynamics with spins in semiconductor quantum dots.

The low temperature operation of quantum computing devices implies developing characterization protocols, from extensive statistical tests to targeted device screening at cryogenic temperature. This paper reviews major integration constraints arising in linear Si quantum dots arrays and their implication on both the device operation and electrical characterization.

We present a status of FDSOI transistors electrical characterization for very low temperature operation. We highlight in particular singular transport and thermal effects occurring at low T. We also present the physical and analytical models associated with various characteristic electrical parameters, paving the way towards cryogenic compact models.

Scalability is one of the biggest advantages of silicon spin qubits over other platforms, making them very promising candidates in the quest for quantum computing. In this work we approach the regime of interest for large-scale qubit integration, showing that we can deliver high electrostatic coupling control and individual tunability over an array of quantum dots (QDs). To do this we use FDSOI devices fabricated with 2-metal gate levels in an industry-compatible CMOS process. We operate them at 100mK, and in a dot-configuration where large control on tunnel barriers is leveraged. In the many-electron regime, we observe the transition of quantum dot array from single- to triple-dot configurations. Moreover, in the few-electron regime, we demonstrate the effective and in-situ modulation of the tunnel coupling between two adjacent QDs.

This paper presents an electrical characterization and a compact modeling of FD-SOI four-gate qubit MOS devices, carried out at room temperature and in linear regime. The main figures of merit are extracted from average drain current curves using Y – function method. Poisson solver-based simulations are performed to interpret the experimental data, in particular the influence among gates and the effective channel length modulation. Furthermore, a drain current matching analysis between gates is conducted, and the main variability parameters are extracted. Our results, despite the unconventional device engineering, show a variability performance comparable to the state-of-the-art 28nm FD-SOI technology. Finally, a Lambert function based model is developed to validate both the electrical and statistical characterization. It is assumed, according to the experimental data, that the four gate device can be modeled as the series of four identical and independent transistors. Including the contribution of source and drain access resistance it has been possible to reproduce the device behavior at high external gates voltages.

Operating Si quantum dot (QD) arrays requires homogeneous and ultra-dense structures with aggressive gate pitch. Such a density is necessary to separately control the QDs chemical potential (i.e. charge occupation of each QD) from the exchange interaction (i.e. tunnel barriers between each QD). We present here a novel Si quantum device integration that halves the effective gate pitch and provides full controllability in 1D FDSOI QD arrays. The major advantages of this architecture are explored through numerical simulations. Functionality of the fabricated structure is validated via 300K statistical electrical characterization, while tunnel-coupling control is demonstrated at cryogenic temperature.

Semiconductor-based architectures where quantum information is encoded in the spin degrees of freedom of electrons or holes form an appealing platform for quantum computing. Here we present the current state-of-the-art and discuss prospects and challenges at scientific and technological level.

Si spin qubits are very promising to enable large scale quantum computing as they are fast, of high quality and small.However, they are still lagging behind in terms of number of qubits.Indeed there are material and integration challenges to be tackled before fully expressing their potential.

We present recent progress in the implementation of scalable schemes for spin qubit readout in one dimensional quantum registers based on fully-depleted silicon-on-insulator (FDSOI) technology. We compare two schemes both based on rf gate reflectometry. The first one, denoted as dispersive readout, minimizes the device overhead thereby facilitating scale-up to large qubit registers. The second one, denoted as charge-sensing readout, requires additional readout components but is less sensitive to the strength of the interdot coupling facilitating operation in the few-electron regime. We demonstrate single-shot charge sensing with a fidelity of 97% in 5 μs. Finally, we propose a scalable device architecture for linear qubit registers relying on charge-sensing readout.

We discuss the status, challenges and perspectives of "Quantum CAD" for the design and exploration of spin qubits. We highlight the similarities and differences with conventional TCAD for micro-electronics, and focus on design, physics and variability of silicon-on-insulator qubits as an illustration.

The built-in bipolar junction transistor (BJT) of a BIMOS fabricated in 28 nm ultra-thin body and BOX (UTBB) fully-depleted silicon-on-insulator (FD-SOI) high-k metal gate technology is investigated in common-emitter mode and in built-in metal-oxide-semi-conductor field effect transistor (MOSFET) off-state. In the weak V-BE regime, field-effects dominate, generating a negative base current and making the current gain beta(0) meaningless. For V-BE high enough, the BJT works normally but with a very low gain below 1.

Neuromorphic computing is an emerging field of investigation for new algorithm solutions and daily life applications. We investigate a novel design to achieve a spiking neuron operator which uses BIMOS transistor combined with a capacitor and a NMOS bias transistor. The devices are integrated on thin silicon film in 28 nm high-k/metal-gate standard CMOS technology. The proof of design is introduced through 3 dimensional technology computer-aided design (3D TCAD) numerical simulations, and then validated by electrical characterization of the 2T/1C demonstrator. High spiking performance with very low power consumption is obtained. In addition, the spiking neuron design benefits from intrinsic electro-static discharge (ESD) robustness.

GDNMOS (Gated Diode merged NMOS) and GDBIMOS (Gated Diode merged BIMOS) were fabricated using the 28 nm node ultra-thin film UTBB FD-SOI high-k metal gate CMOS technology. The anode current and voltage were measured and simulated for a high number of variants with different connectivity conditions on the terminals. The devices are reconfigurable and promising for high voltage ESD protection applications.