The Computing-In-Memory (CIM) paradigm offers a promising solution to the memory-wall bottleneck that limits conventional Von Neumann architectures. By performing data processing at the same physical location where the data are stored, CIM-based architectures minimize costly data movement and drastically improve energy efficiency. When implemented with Ferroelectric Field Effect Transistors (FeFETs), additional advantages from the non-volatility, fast switching, and low operating voltage of FeFETs are added. However, the widespread adoption of FeFETs is limited by their poor endurance, which is overcome by a Back End of the Line (BEoL) integration of FeFET-2, where a ferroelectric capacitor (FeCAP) is wired to the gate of a CMOS transistor providing high endurance compatible with low-power edge applications. These properties enable dense, low-power, and high-speed matrix operations essential for AI workloads. As a result, FeFET-2-based CIM accelerators offer a promising solution for energy-efficient, high-performance AI at the edge. The Ferro4EdgeAI project aims to develop an ultra low-power, scalable edge accelerator for AI, targeting a significant gain in energy efficiency with respect to state-of-the-art AI hardware accelerators. To attain this, our project focuses on innovation all along the value chain from materials, physic concepts, device architecture, integration technologies, and accelerators in a holistic design space exploration approach.

This work proposes a Verilog-A SPICE model for Ferroelectric Random Access Memories (FeRAM) device to manage major loops hysteresis including different ferroelectric distributions of Preisach-like approach. Our model is validated on different circuit simulators in different configurations such as 16kbit 1T-1C FeRAM array to demonstrate the model's capability in terms of robustness.

The European FAMES Pilot Line addresses a set of technologies including fully depleted silicon-on-insulator technology advanced nodes and embedded non-volatile memories. This paper addresses these two technologies and the programs planned to help designers to use these technologies at their best. The specific electrical properties of FD-SOI devices, are discussed, both in terms of transistor modelling and process highlighting the levers exploited to boost the performance of the future 10-7nm nodes will be also highlighted. The paper also address embedded Non-Volatile Memory (eNVM) devices integrated in the BEOL of advanced FD-SOI CMOS technologies with the aim to open opportunities for disruptive IC architectures and designs using the most appropriate eNVM for the considered applications. OxRAM, FeRAM, BEOL FeFET and MRAM are addressed in FAMES and in the paper and potential new applications are discussed. Finally, the way these technologies are provided to designers through training programs is described.

In this paper, we propose a new charge-based sensing scheme for read operation in ferroelectric random access memory (FeRAM) arrays. Experimental demonstration on 16kbit up to 256kbit Hf x Zr 1-x O 2 (HZO)-based one transistor - one capacitor (1T-1C) FeRAM arrays reveals that this capacitive trans-impedance amplifier (CTIA)-based sensing has several key advantages over conventional voltage-based sense amplifiers (SA). The major benefits of this innovation are i) a median memory window (MW) as large as 1000mV which is ii) quasi-independent of array size, overcoming the well-known MW closure with bitline capacitance (C BL ) increase observed in FeRAM arrays with conventional voltage-based sense. This new sensing scheme is expected to be of most importance for large HZO FeRAM arrays integrated at advanced nodes, as it enables to increase memory bank size.

7nm HZO-based 2D ferroelectric capacitors $(\mathrm{C}_{2\mathrm{D}})$ down to $0.0028\mu \mathrm{m}^{2}$ area were successfully integrated in the BEOL of 22nm FDSOI node, with $2.\text{Pr} > 10\mu \mathrm{C}/\text{cm}^{2}$ and extrapolated breakdown-limited endurance $> 10^{13}$ cycles. $\mathrm{C}_{2\mathrm{D}}$ exhibit a strong layout-dependent remanent polarization that is consistent with biaxial stress reduction. $16\text{kbit}\ 1\mathrm{T}-1\mathrm{C}_{2\mathrm{D}}$ FeRAM arrays were designed and fabricated to quantitatively assess the memory window (MW) dependence with capacitor and transistor dimensions as well as operating voltages. 0 bitfail up to $10^{10}$ cycles is demonstrated on these 22nm FeRAM arrays at 2.4V, with median MW larger than 100mV. In order to reduce FeRAM bitcell footprint, 3D-based FeCap $(\mathrm{C}_{3\mathrm{D}})$ are also demonstrated, leading to 2.Pr up to $140\mu \mathrm{C}/\text{cm}^{2}$ (normalization by footprint) with projected median MW at array level of 600mV at 1.5V for $0.047\mu \mathrm{m}^{2}\ 1\mathrm{T}-1\mathrm{C}_{3\mathrm{D}}$ bitcell.

The Memory Window (MW) of BEOL-integrated Si:HfO 2 -based 16kbit ITIC FeRAM arrays is shown to be significantly improved (×3) by etching the ferroelectric (FE) film of the Ferroelectric CAPacitor (FeCAP). To estimate the MW evolution in larger arrays at advanced technology nodes, a Preisach current-based compact model is developed, calibrated on measured FeCAP electrical characteristics and validated at various operating voltages. Electrical simulations of an elementary ITIC 16kbit FeRAM array-like structure using Siemens Eldo show that scaling the transistor (1T) at advanced technology nodes can be beneficial for the MW. FE film thickness reduction below 10nm will also be requested for low voltage applications.

This work demonstrates for the first time the 3D sequential integration of CMOS over CMOS with advanced metal line levels (28nm Cu + ULK). The bottom tier consists of a 28nm FDSOI industrial wafer with 4 metal lines. A bevel contamination wrap module allows the return of the wafer to Front End Of Line (FEOL) environment required for achieving high performance top FET Si CMOS processing. Additionally the doped poly-Si ground plane introduced enables top FET dynamic back-biasing and effective DC and HF isolation with underlying metal lines. Finally, this 3DSI platform demonstrates functional top, bottom, and 3D ring oscillators as well as a pixel with single exposure flicker-free High Dynamic Range capability obtained thanks to the stacking of an additional circuit over a bottom 3T-pixel.

This paper presents an experimental demonstration of a hybrid FeRAM/RRAM synaptic circuit. The circuit incorporates Metal-Ferroelectric-Metal stacks, which exhibit native FeRAM behavior and function as RRAMs after undergoing a forming operation. By leveraging the unique advantages of FeRAMs, such as ultra-low switching energy, in combination with the non-disruptive (infinite) reading capability of RRAMs, this circuit enables efficient on-chip inference and learning at the Edge.

In [1] we reported for the first time a frequency modulation method to control the conductance level in PCM cells. This increases the programming reliability of PCM, which is crucial for neuromorphic applications. We provided a physical picture and a physics-based analytical model to link the programming frequency to a target conductance. In this new report, we are the first to successfully demonstrate frequency modulation on 16kbit PCM array in a real case scenario. We first convert synaptic weights in target conductivities, next we translate them into modulation frequencies and transfer values to the PCM array. Eventually, we evaluate the accuracy of a test CNN (Convolutional Neural Network) based on pre-programmed PCM values for recognizing handwritten digits from the MNIST database. We evaluate different redundancies schemes and show up to 90% accuracy and high reliability. We complement our model after careful characterization of the distribution in the programming error (|G target -G pcm |) and show that we can fully predict the inference accuracy. PCM drift characterization shows good data stability over 24 hours at room temperature. Eventually we propose a block schematic of a FSM (Finite State Machine) to implement the frequency modulation on-chip, showing the benefit of such an approach as ease of design.

Embedded resistive random access memories (RRAM) are commonly written using voltage programming scheme. In this work, we study the device performance under an alternative programming approach. Utilizing the parasitic line capacitance combined with a current source, this scheme lowers the required programming current by a factor of 10 for a given conductance level. This effectively reduces writing energy and alleviates constraints on integration density due to electromigration and IR drop. The proposed scheme is demonstrated on 130nm CMOS technology. The measurements show a low raw bit failure rate of $5.10^{-{5}}$ through 200k cycles. The read margin can be widened up to $25~\mu \text{A}$ using a write-verify strategy. These metrics highlight the efficiency of the proposed scheme with respect to the conventional voltage techniques.

CMOS Imagers have adopted 3D integration using Back-Side Illumination (BSI) technology, with 2 CMOS layers assembled using Wafer-to-Wafer and advanced Hybrid Bonding technology. Targeting innovative AI and Machine Learning application, for offering AI processing at the edge within the image sensor itself, this paper presents some new 3D design and technology solutions in order to build a 3-layer Smart Imager. The hybrid bonding technology for assembly of multi wafers with a capability below 1 µm pitch is shown as well as Through Silicon Via (TSV) of 2 µm pitch compatible with hybrid bonding. To offer Design Technology Co-Optimization (DTCO) capabilities, a Place & Route methodology is proposed with the associated PDKIT to benefit of fine pitch interconnects.

We present for the first time Si-doped HfO2-based OxRAM 16kbit arrays integrated in the BEOL of 28nm FDSOI CMOS, targeting low cost and low power embedded applications. Excellent LRS/HRS raw distributions are reported on 1T-1R 16kbit arrays with zero bit-fail up to 105 cycles, using core logic (GO1) selector transistors. The OxRAM compatibility with GO1 transistors paves the way to arrays with minimum bitcell area of $0.066\ \mu \mathrm{m}^{2}$ at $125\mu \mathrm{A}$ programming current. We also demonstrate direct correlation between transistor compliance current variability within the 1T-1R array and the LRS distribution. This result indicates that the intrinsic LRS variability is smaller than the measured one. SPICE Monte-Carlo simulations confirm the large compliance current dispersion measured on transistors designed at minimum gate length and show path to improve even further the LRS distribution and hence the OxRAM memory window.

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.

3D sequential integration (3DSI) is envisioned for highly miniaturized smart imagers and fine pitch logic and memory imbrication. This paper describes partitioning in 3DSI and design methodologies. A status is also done on low temperature processes and device performance adapted for these applications (i.e. digital $\mathrm{V}_{\text{DD}}\leq 1\mathrm{V}$ and analog $\mathrm{V}_{\text{DD}}\geq 2.5\mathrm{V}$ devices).

This paper discusses the mixed-signal circuit design in a novel monolithic (sequential) 3D process. The goal of this work is to explore a novel multi-process sequential 3D technology with the state-of-art 3D interconnections density of 2 × 10 7 via/mm 2 and we report our first impressions. The paper discusses the design of a 3-bit SAR and a 3-bit Flash ADCs, where we have partitioned digital and analog parts in a new under test shrink 65nm technology stacked over a 28nm FDSOI process. The 3D connection density of the applied process is almost on par with the horizontal connection densities within a tier. This fact will enable what we refer to as ‘Systems-in-Cube’ (SinC), i.e. fine-grained volume implementations where individual transistor of small functional blocks can be distributed across 3D tiers. We estimate an area reduction of about 40% compared to a pure 2D 28nm realization of the same circuits and 80% compared to an equivalent 2D 65nm implementation for a ‘balanced’ mixed signal design. Moreover, we also estimate that this would result in an overall price reduction for these circuits in a mature commercial sequential 3D process.

Monolithic 3D (M3D) stands now as the ultimate technology to side step Moore's Law stagnation. Due to its nanoscale Monolithic Inter-tier Via (MIV), M3D enables an ultrahigh density interconnect between Logic and Memory that is required in the field of highly energy efficient 3D integrated circuits (3D-ICs) designed for new abundant data computing systems. At design level, M3D still suffers from a lack of commercial tools, especially for Place and Route, precluding the capability to provide signoff M3D GDS. In this paper, we introduce M3D-ADTCO, an architecture, design and technology co-optimization platform aimed at providing signoff M3D GDS. It relies on a M3D Process Design Kit and the use of a commercial Place and Route tool. We demonstrate an area reduction of 23.61 % at iso performance and power compared to a 2D RISC-V micro-controller based System on Chip (SoC) while creating space to increase (2x) the RISC-V instruction memory

Al 2 O 3 based Conductive Bridge RAM (CBRAM) is co-integrated with an optimized Ge-Se-Sb-N based back-end selector in 1S1R memory arrays for low voltage and advanced CMOS compatibility. Electrical characterization is performed to extract device features, showing forming free behavior, ~3.5V maximum operating voltage, s table 2 decades for I on /I off during 10 7 cycles, ~1V reading voltage margin and moderate leakage current. Compatible with 100kbit sector size, this optimized stack is found very promising for embedded applications on advanced process nodes. Indeed, design exploration on a 28nm core process shows that peripherals can be designed with middle voltage MOS, fitting best with low voltage 1S1R cross-point array and leading to reduced overall memory area.

OxRAM technology is one of the strongest candidates for embedded solutions at scaled nodes (<; = 40nm), thanks mainly to its low manufacturing cost. To scale the bitcell, both the OxRAM and the selector device must be taken into account. In this paper we first show how the OxRAM reliability is impacted by scaling down to 30nm in diameter, focusing on the forming voltage, BER and data retention on a large statistics (4kbit arrays). Several strategies are provided to reduce the BER leading to a projected 10 -6 BER result. We then illustrate how thin gate oxide transistors (GO1/SG) can meet the OxRAM high voltage requirement as the memory bit approaches 100nm diameter, and we demonstrate an OxRAM (120nm) co-integration with FDSOI transistors with remarkably good performance (endurance up to 10 7 cycles on single bit). Eventually we illustrate a design example of OxRAM embedded solution in 40nm, 32Mb+ECC, featuring a 0.120μm 2 bitcell and a 170nm OxRAM cell.

Design of 3D ICs is mainly done in separated design environments for each tier, assuming that communication channels between tiers are user-defined and fixed at the beginning of the design process. Suitable for 3D stacking based on TSV or Hybrid Bonding technologies because of low granularity of these 3D interconnect elements, this methodology becomes less effective for 3D sequential technologies once trying to integrate Monolithic Inter-tier Vias (MIVs) with higher density (around 1.10 8 vias per mm 2 ). In this paper, we describe a methodology to create a unified design environment for 3D sequential technology by merging Process Design Kits (PDKs) of different technologies attached to different tiers. Main advantage of this methodology is that designing a 3D circuit may no more require several design environments, thus simplifying simulations, verifications and layout finishing. As a proof of concept, we designed and taped-out a RISC-V processor with logic on memory architecture using LETI CoolCube 28nm FDSOI on top of ST 28nm FDSOI technology.