The adoption of 5G mmWave is upon us, with major cell phone companies having introduced phones with mmWave capabilities and major US cellphone providers building their infrastructure out. Parts manufactured using Globalfoundries 45RFSOI technology have made significant traction in the infrastructure space. A good part of the success of this technology is based on the excellent high frequency performance of the thin oxide device, the high resistivity substrate and the high voltage support enabled by the use of stacking in SOI technologies. In this paper we introduce a new transistor developed to improve the output power of mmWave power amplifiers (PA). It demonstrates ∼ 1.2X increase in maximum voltage, reduced linear mode resistance and ∼20% increases in fMAX to >400 GHz

We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both gate-contact (CB) to source-drain local interconnect (LI) shorts and the LI-contact (CA) to gate shorts is the shape of the LI cap. A trapezoid-shaped oxide (SiO 2 ) LI cap with an appropriate taper angle eliminates shorting between the contacts in the gate and source-drain region. We further demonstrate that this oxide LI cap is fully compatible with Cobalt (Co) metallization with a novel selective tungsten (W) growth process. Additionally, this process enables the SRAM cross-couple (XC) in the same metallization level, eliminating the need for an upper level wiring and greatly simplifying routing in the SRAM cell.

SiGe FinFET has been explored for its benefit of high current drivability provided by channel strain [1-5]. We have demonstrated SiGe CMOS FinFET at 10nm technology ground rules including epitaxial defectivity control, DC performance and reliability benefit [6-8]. One concern of SiGe FinFET is channel strain relaxation by fin cut process [9] inducing local layout effect (LLE), which is crucial for product design. In this paper, we thoroughly examined LLE in SiGe pFinFET and explored its mitigation techniques. Two techniques are proposed and demonstrated successful LLE mitigation, which drives forward SiGe FinFET insertion to technology.

In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc < 2.2×10 −9 Q-cm 2 on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional approach of high in-situ doped epi and the novel SPE processes are systematically studied on device and ring oscillator (RO) level. Clear improvement in the RO delay is accomplished by the novel dual SPE process on the CMOS flow. Stronger performance benefit is demonstrated with smaller contact sizes towards future CMOS technology nodes.

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

As transistor size continues to shrink, SiO2/polySi has been replaced by high-k/metal gate (HKMG) to enable further scaling. Two different HKMG integration approaches have been implemented in high volume production: gate first and gate last—the latter is also known as replacement gate approach. In both integration schemes, getting the right threshold voltage (Vt) for NMOS and PMOS devices is critical. A number of recent studies have shown that Vt of devices is highly dependent on not just the as deposited material properties but also on subsequent processing steps. In this work, the authors developed an advanced high-resolution electron energy loss spectroscopy method capable of accurate measurement of material composition on device structures. Using this method, the nitrogen and oxygen concentration at the HKMG interface on p-channel field-effect transistor (PFET) transistors with slightly different metal gate stacks were studied. The authors demonstrated that the correct amount of nitrogen and oxygen at the HKMG interface is required to get the right PFET Vt.