A new methodology to accurately simulate the Photon Detection Efficiency and the Jitter tail of SPAD devices is presented. This method first relies on the use of the electric field lines to mimic the carriers' trajectories. A model for impact ionization and avalanche probability is then used on the obtained lines to simulate the probability of avalanche, coupled with the optical absorption, the PDE is then extracted. Finally, an advection-diffusion model is used to simulate the drift and diffusion of carriers within the device, which leads to the timing jitter due to the transport time from the photogeneration spot to the avalanche region. The results obtained numerically are compared with an extensive series of measurements and show a good agreement on a wide variety of device designs.

A new method to reliably simulate the PDE and jitter tail for realistic three-dimensional SPAD devices is presented. The simulation method is based on the use of electric field lines to mimic the carriers’ trajectories, and on one-dimensional models for avalanche breakdown probability and charges transport. This approach allows treating a three-dimensional problem as several one-dimensional problems along each field line. The original approach is applied to the McIntyre model for avalanche breakdown probability to calculate PDE, but also for jitter prediction using a dedicated advection-diffusion model. The results obtained numerically are compared with an extensive series of measurements and show a good agreement on a wide variety of device designs.

We propose a straightforward technique to increase the near-infrared photo-detection efficiency (PDE) in single photon avalanche photodiodes (SPAD) manufactured in CMOS industrial foundries, without any change in the usual semiconductor process flow. The mask used for the photolithography of shallow trench isolation (STI) is modified to generate sub-wavelength patterns in the silicon area illuminated by incident light. The dimensions of the nanostructures are easily accessible by standard UV-lithography. The resulting improved anti-reflection effect and absorption in Si due to diffraction can provide up to 50% relative gain in PDE at 850-nm wavelength in simulation, while 25% gain is demonstrated in this paper, without degrading the median dark count rate (DCR) at ambient temperature. Some performance degradation is observed with the appearance of after-pulses, possibly due to the absence of surface passivation specific to the nanostructures in this first demonstration. The effect is angularly robust, relatively broadband, and relatively tolerant to fabrication errors. High PDE enables longer range or lower power consumption in applications for distance measurement with an active illumination, such as proximity sensing, 3-D ranging, or 3-D imaging.

We present theoretical simulation and experimental results of a new colour pixel structure. This pixel catches the light in three stacked amorphous silicon photodiodes encompassed between transparent electrodes. The optical structure has been simulated for signal optimisation. The thickness of each stacked layer is chosen in order to absorb the maximum of light and the three signals allow to linearly calculate the CIE colour coordinates [1] with minimum error and noise. The whole process is compatible with an above integrated circuit (IC) approach. Each photodiode is an n-i-p structure. For optical reason, the upper diode must be controlled down to 25 nm thickness. The first test pixel structure allows a good recovering of colour coordinates. The measured absorption spectrum of each photodiode is in good agreement with our simulations. This specific stack with three photodiodes per pixel totalises two times more signal than an above IC pixel under a standard Bayer pattern [2,3]. In each square of this GretagMacbeth chart is the reference colour on the. right and the experimentally measured colour on the left with three amorphous silicon photodiodes per pixel. (C) 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

We demonstrate a back illuminated colour image sensor with a 1.4μm pixel pitch. A novel backside adapted pinned deep diode on n-substrates has been developed and characterized in order to achieve an improved colour separation. High quantum efficiency around 60% in the visible light spectrum has been attained whereas the other parameters stay in line with standard front side illuminated image sensors. Introduction: Backside illuminated (BSI) CMOS image sensors have been reported as a possible solution for the 1.4μm pixel pitch and below [1]. Beside the multipl e advantages, like 100% fill factor, lower optical st ack and higher metal packaging density [2-4], the BSI sensors also point out several design and process challenges, like the backside to frontside alignmen t and the electrical crosstalk [3-4]. We have realize d a colorized BSI CMOS image sensor demonstrator with a 1.4μm pixel pitch in 1T5 architecture and a deep pinned photodiode on n-substrates for effectiv interpixel junction isolation, resulting in crossta lk improvement. The quantum efficiency (QE) has been improved by a factor of 2 in comparison to a simple frontside conventional diode, which is illuminated from the backside. The other parameters are in line with standard front side illuminated image sensors. Pixel Design: The front-end design of the backside illuminated image sensor is based on a 0.13μm CMOS process. The backend metallization has been realized in 90nm copper based design rules. The pixel architecture consists of a pinned photodiode with transfer gate for reset noise cancellation due to correlated double sampling (CDS). Each pixel has a diode and a transfer gate transistor (TG). In order to increase the fill factor, four pixels are regrouped to one sensi ng node, which is connected to a RESET transistor and to a source follower (SF) transistor. With the READ transistor placed in the column circuitry, the aver ge number of transistors per pixel is 1.5 (1T5 architecture, see figure 1). Process& Experiments: The process flow is summarized in figure 2: After t he CMOS imager frontend and backend realisation on SOI substrates a waferbonding layer (WBL) is deposited and prepared for wafer bonding on a support wafer. Once the wafers are bonded and backside thinned, an anti-reflective coating is deposited, the pads are reopened from the backside and subsequently colour filters (CFA) and microlenses are processed. The alignment of the backside CFA and microlenses to front side layers was controlled by standard production FRAME-inFRAME overlay controls (figure 3) and mappings (figure 4). The circuit transfer process (bonding a nd thinning) has been improved in order to decrease th e layer deformation after transfer. A layer deformati on, which is compatible with the colorization alignment specs, has been achieved thanks to these improvements (figure 4). Three process approaches have been tested in order to improve electrical crosstalk, which is inherent to backside illuminated image sensors: thin p-epi laye rs, graded p-epi layers and a novel backside adapted pinned deep diode, realized on n-substrates. If the photo sensitive layer (epi-layer) gets thinn er, the photo generated electrons have to cover a short er distance in order to reach the diode. Thus they hav e a lower possibility to diffuse into the neighbouring pixels. Figure 5 shows the comparison between a 1.0 and 1.5μm epitaxial layer . We observe a decrease of crosstalk for thinner substrates for the benefit of higher quantum efficiency. Nonetheless this approac h of frontside conventional photodiode still induces too much QE losses. Likewise in combination with frontside conventional photodiodes, doping gradients have been realized by adding boron during the epitaxial growth process. The boron doping gradient (see figure 6), creates a n electric built-in field, which pushes the photogenerated electrons to the photodiode. The introduction of the graded p-doping profile results in a limited crosstalk improvement. The modulation transfer function (MTF) at Nyquist/4 has been improved by at least a factor of 2 in the visible spectrum. A novel backside adapted pinned deep diode architecture on n-substrates has been simulated (figure 7) and processed. This deep diode can be subdivided into two parts: A first collecting and storing diode on the illuminated side, with a natur l built-in electrical field. This first diode guarant ees the collection of photogenerated electrons to the stora ge diode (figure 8). The storage diode is located at t he opposite of the illuminated side. The interpixel isolation has been realized by p-implants at multip le energies and doses, in order to create a junction isolation wall. These isolation walls are 4-11 time s more effective by replacing the standard p-substrat e by an n-substrate (figure 9). Pixel performances of the pinned deep diode on nsubstrates: The conversion gain of the image sensor is 70μV/e . We notice a significant improvement of the QE by the introduction of the deep diode on n-substrates. The QE increases to 60% in the blue spectrum and to 50% in the green spectrum, attended by a corresponding decrease of crosstalk, as can be seen in (figure 10). We attribute these enhanced performances to the effective interpixel isolation and to a very good drift of the photogenerated electron s t the diode. The red signal can be improved by 10% QE by means of a broadband antireflective filter (figure 11). Figure 11 also shows the extrapolation of QE gain in case of a thicker epitaxial layer at 4μm instead of 2μm. It was assumed that the crosstalk increases in the same relation as the absorption. T his simulation shows that the QE can be higher than 65% for the blue, green and red spectrum due to an improved antireflective coating layer and a higher absorption in thicker epitaxial layers. The full we ll diode saturation charge is as good as for standard frontside diode. The dark current is 1e /s at 25°C. The low dark current has been achieved thanks to dedicated frontside and backside process steps such as p pinning layer and thermal treatment. Thanks to a very good charge transfer, the lag is below the measurement threshold. Figure 12 shows a colour picture, taken with the discussed image sensor demonstrator with deep diode on n-substrate at 500lux, 15 frames per second, f-number 2.8. The main image sensor parameters are summarized in table 1. Conclusion: We have demonstrated a back illuminated colour image sensor with a 1.4μm pixel pitch. Due to the introduction of a deep diode in n-substrates, resul ting in an effective interpixel isolation and an enhance d drift of photogenerated electrons to the diode, we obtained a significant improvement of QE with 60% in the blue spectrum and 50% in the green spectrum. The application of a broadband antireflective filte r and thicker epi substrates will lead to a QE higher than 65% in the blue, green and red spectrum. Acknowledgements: We would like to thank TraciT Technologies for wafer bonding studies. Likewise we would like to express our gratitude to the CEA Leti process teams and the STMicroelectronics process and characterization teams for fruitful discussions, wa fer processing and characterization. References: [1] JungChak Ahn et al, “Advanced image sensor technology for pixel scaling down toward 1.0μm”, p.275, IEDM 2008 [2] S. Iwabuchi et al., “A Back-Illuminated High Sensitivity Small-Pixel Color CMOS Image Sensor with Flexible Layout of Metal Wiring”, p.302, ISSCC 2006 [3] Tom Joy et al, “Development of a ProductionReady, Back-Illuminated CMOS Image Sensor with Small Pixels”, p. 1007, IEDM 2007 [4] Jens Prima et al, “A 3Mega-Pixel backilluminated image sensor in 1T5 architecture with 1.45μm pixel pitch”, p.5, IISW 2007 Figure. 1: 1T5 pixel schematic SOI wafer CMOS Imager Process – FE 130nm – BE 90nm Cu Wafer Bonding Layer (WBL) Deposition and Preparation Wafer bonding and backside grinding Anti-reflective-coating (ARC) Pad opening Color Filters and Micro-Lens processing Figure 2: Process flow Precedent layer Subsequent layer Figure 3: Left: Principle of FRAME-in-FRAME overlay control; Right: Overlay control of backside layer to frontsi de layer 1μm Figure 4:Mapping of overlay control, showing a laye r deformation of the bonded wafer, which is compatib le to colorization alignment 0 5 10 15 20 25 30 35 380 400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 700 wavelength [nm] Q E [% ] Blue, 1.0μm Gr_R, 1.0μm Red, 1.0μm Blue, 1.5μm Gr_R, 1.5μm Red, 1.5μm Figure 5: Comparison of QE of 1.0 and 1.5μm thick e pitaxial SOI substrates (conventional diode) 1E+15 1E+16 1E+17 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Depth [μm] C on ce nt ra tio n [a t/c m 3] ... pixel specific PWELL grad Boron= 0.5 decades/2μm Figure 6: SIMS of sample with a boron gradient of 0 .5 decades. The corresponding electrical drift field is 20 mV/μ m

We investigate the possibility of recovering spectral information using a multilayer structure realized through microelectronics technologies and compatible with a matrix arrangement. The structure is made of photoabsorbing layers, acting as local photodetectors, alternating with transparent layers. The whole structure lies on a reflective surface. A stationary wave containing the spectral information of the source is generated within the structure. We determine the intensity of the stationary wave at any position, taking into account absorption and multireflections at each transition as well as the signal detected by the photoabsorbing layers. The model forecasting the detected signal is then validated using p-i-n diodes of different thicknesses made of hydrogenated amorphous silicon (a-Si:H) encompassed between indium tin oxide (ITO) electrodes. The detected signal depends on the wavelength of the incident light, the thickness of the detecting layer, and the latter's position within the structure. A specific spectral response can then be associated to each photoabsorbing layer. We show how spectral information can be retrieved from this kind of structure in the visible spectrum range.

This paper presents an innovative 3D architecture capable of overcoming pixel miniaturization drawbacks. Back-illuminated photodiodes are realized on a first silicon layer, while readout transistors are located on a second silicon layer. Implications of a sequential integration are evaluated in the perspective of low noise pixel performances with a comprehensive study on: 1/ setting the thermal budget limit to 700degC to preserve transfer gate performances, 2/ transferring high quality SOI by direct bonding 3/ processing HfO 2 /TiN fully depleted transistors, exhibiting noise levels close to standard 2.2 mum pixels, with improvement solutions.

A 3Mega-Pixel back illuminated image sensor in 1T5 architecture and 1.45μm pixel pitch has been successfully developed and characterized. A high quantum efficiency over 60% in the visible light spectrum and a low dark current of 1e /s at 25°C have been achieved due to dedicated frontside and backside process steps such as antireflective layer adaptation, p + pinning layer and thermal treatment. Introduction: CMOS image sensors are gaining a high influence since several years. The main challenge consists in shrinking the pixels without decreasing the pixel performances, as the optical stack and the metal wiring over the surface reduced diode cause optical efficiency issues [1, 2]. The realization of a backilluminated image sensor offers a fundamental solution, as the backend stack is located under the photodiode [1-3]. We demonstrate a 3 Mega-Pixel back-illuminated image sensor with a 1.45μm pixel pitch in 1T5 architecture, which has a mean dark current of 1e/s at 25°C and a quantum efficiency (QE) of over 60% in the visible light spectrum. Pixel Design: The backside illuminated 3MP image sensor with a 1.45μm pixel pitch has been realized in a 0.13μm front-end CMOS based process. The backend metallisation was processed in 90nm copper based design rules [4]. The principal pixel architecture is a pinned fully depleted noiseless photodiode with transfer gate and reset noise cancellation thanks to correlated double sampling (CDS). Several transistors are shared between neighbouring pixels, resulting in 1T5 pixel architecture [4]. A pixel schematic is shown in figure 1: each pixel has a diode and a transfer gate transistor (TG). In order to increase the fill factor, four pixels are regrouped to one sensing node, which is connected to a reset (RST) transistor and to a source follower (SF) transistor. Process& Experiments: The process is realized on silicon on insulator (SOI) starting material. Several SOI thicknesses have been evaluated in order to find an optimum between quantum efficiency and crosstalk. Dedicated p implants are implanted in the pixel area. A vertical p implant isolates the pixels from each other, resulting in a lower crosstalk and higher quantum efficiency. Figure 2 shows a relative increase of 20% quantum efficiency with the introduction of the specific p + implant. In a standard CMOS imager the diode surface potential is pinned to 0V and the photogenerated holes are evacuated by the substrate. On the SOI substrate the diode surface pinning and the hole-evacuation is provided by an additional contact on a p + implant. The backend consists in 3 metal layers. As the chips are illuminated from the backside, metal lines are allowed to cross directly above the diode area [3]. Furthermore the dielectric backend stack does not have to be optically optimized in terms of total thickness and material composition. After the final metal layer, a passivation layer and subsequent wafer bonding layer (WBL) are deposited. The WBL is planarized and a support wafer is bonded to the processed wafer. Afterwards the processed wafer is back-grinded. The backside surface is covered by an antireflective coating in order to avoid light losses by reflections. Figure 3 shows the simulated transparency with and without antireflective layer. The pads are reopened through the active silicon layer and finally deposited and patterned aluminium in the pads provides a standard surface for test and package purposes. In the next development steps color filters will be realized on the sensor, which is monochrome without micro-lens for the time being. The process flow is summarized in figure 4. Pixel performances: The conversion gain of the image sensor is 66μV/e . The quantum efficiency (QE) has been evaluated as a function of the SOI thickness. Figure 5 shows that a QE gain for wavelength >460nm can be observed for a thick SOI layer, as too thin silicon layers cannot absorb the entire light quantity of longer wavelength according to the absorption law. The Modulation Transfer Function (MTF) for different wavelengths is presented in figure 6. A decrease of the MTF, which is equivalent to an increased crosstalk, can be observed for shorter wavelengths. As the blue light is absorbed near the surface, the photogenerated electrons have to cover a longer distance in order to reach the diode and thus have a higher possibility to

The authors report record performances for the reliability of amorphous silicon (a-Si:H) photosensor under high flux illumination. A fully functional VGA (3.0 mum pitch) image sensor, which can withstand 90 suns (= 9 Mlux) during 26 ks, was realized by the optimization of a-Si:H parameters, the pixel structure and the reading voltage

In this paper we present the first demonstration at LETI infrared laboratory of a megapixel HgCdTe MWIR focal plane array with a 15mum pitch. The detectors were interconnected by indium bumps to the CMOS readout circuit. The design of these interconnections has been adapted from the standard CEA-LETI process to achieve resolution and uniformity required by the reduced pitch. Because of the mismatch of thermal dilatation coefficients between the substrate and the HgCdTe,. specific developments were necessary in order to achieve the hybridization process with an extremely reduced amount of defaults. The readout circuit was designed in a 3.3V/0.35mum CMOS technology. Its main features were to allow the validation of the hybridization and technological processes. A Megapixel IRCMOS has been fully characterized at 77K exhibiting excellent electro-optical performances and an operability greater than 99.8%.

UV–visible imaging systems can be used for various applications, including homeland security systems and mobile phones. Compared to conventional CCD technology, CMOS-based active pixel sensors provide several advantages, such as high integration, low voltage operation, low power consumption and low cost. In this approach, we have recently developed a novel technology using polymorphous silicon. This new material, fully compatible with above-IC silicon technology, is made of nanometer size ordered domains embedded in an amorphous matrix. The quantum efficiency of detectors made of this nano-structured material reach up to 80% at 550 nm and 30% in the UV range, depending of the design and the growth parameters. Furthermore, a record dark current of 20 pA/cm2 at −3 V for 5 μm square pixels has been reached, and the sensor is perfectly linear over more than 6 decades of photocurrent. In addition, this new generation of sensors is significantly faster than their amorphous silicon counterparts.