Carbon nanostructures—such as nanotubes, fullerenes, or graphene sheets—are studied widely in search of future applications in electronic devices. In our work, we demonstrate the possibility of embedding C60 fullerene molecules into a crystalline silicon matrix to form highly confined carbon-δ-layers as well as into an amorphous SiO2 gate stack for possible application as a charge storage device.

An overview of various cleaning procedures for silicon surfaces is presented. Because in-situ cleaning becomes more and more important for nanotechnology the paper concentrates on physical and dry chemical techniques. As standard ex-situ wet chemical cleaning has a significant impact on surface quality und thus device properties, its influence on further processes is also considered. Oxygen and carbon are unavoidable contaminations after wet chemical treatment and therefore we discuss their in-situ removal as one of the main goals of modern silicon substrate cleaning. As surface roughness strongly influences the electrical quality of interfaces for epitaxy and dielectric growth, we concentrate on techniques, which meet this requirement. It will be shown that multi-step thermal sequences in combination with simultaneous passivation of the clean surface are necessary in order to avoid recontamination. This can be achieved not only for ultra hich vacuum but also for inert gas atmosphere. In this case the process gases have to be extremely purified and the residual partial pressure of contaminats such as oxygen and carbon has to be negligible. It will be demonstrated that 800°C is an upper limit for thermal treatment of silicon surfaces in the presence of carbon because at this temperature SiC formation in combination with a high mobility of silicon monomers leads to surface roughness. In addition mechanical stress causes dislocations and crystal defects.

Scanning tunneling microscopy has been used to investigate silicon overgrowth of C60 on the Si(100)-2×1 surface. It can be shown that crystal morphology and quality is highly dependent on temperature and C60 coverage. A C60 coverage of 0.02ML was used to show the initial stage of silicon overgrowth (1.5ML of Si), medium stage with crater formation, crater diminution (10ML of Si) and finally crater overgrowth (100ML of Si). Crystal quality can be improved by annealing of the stack at 750°C for several minutes, but SiC formation at 800°C deteriorates the stack. Segregation of C60 plays an important role already at low coverage. Nevertheless, C60 can be enclosed into the crystal within a few monolayers. This has been proven by STM, TEM and SIMS analysis. Higher C60 coverage leads to 3D islanding, which was proven by STM and LEED, and eventually to polysilicon, shown by STM and TEM. Finally we give a short comparison to the Si(111)-7×7 surface.