We report on the fabrication and characterization of superconducting coplanar waveguide (CPW) resonators based on titanium nitride (TiN) thin films deposited on 200 mm diameter high-resistivity Si(100) substrates. We systematically investigate how deposition conditions, dry-etch power and in-situ resist strip temperature affect morphology, superconducting properties and dielectric losses. By tuning reactive sputtering conditions, three distinct preferred out-of-plane crystal orientations - (111), (200), and a mix of both are achieved. Our results demonstrate that all films exhibit similar minimal two-level system (TLS) losses, with TiN111 exhibiting the lowest median TLS losses _TLS, and greater robustness against reoxidation. The applied structuring process, in contrast, has a far greater influence on the TLS loss than the crystal orientation of the TiN film and, consequently, the intrinsic material properties of the superconducting layer. The lowest TLS losses for all TiN depositions were achieved with a low power etch and low temperature resist strip. An additional buffered oxide etch (BOE) treatment could remove high-loss interfacial oxides at the metal-air (MA) and substrate-air (SA) interface and recover the etch-induced TLS losses. Consequently, TiN resonators exhibiting _TLS values as low as 9.67 × 10^-7 were realized. The corresponding median low-power loss, _LP, amounts to 11.04 × 10^-7, which translates to an internal quality factor approaching one million. These findings highlight the critical role of process induced oxide formation at the MA and SA interfaces in limiting the performance of TiN resonators and provide a scalable, low-loss process compatible with industry-grade 200 mm CMOS qubit fabrication workflows.

Josephson junctions are key elements in superconducting qubits. Their efficient wafer-scale characterization is crucial for process control and optimization, motivating analysis approaches that extend beyond conventional cryogenic measurements. In this work, we demonstrate that room temperature (RT) capacitance and current-voltage measurements, combined with appropriate data analysis, enable extraction of relevant junction parameters such as oxide thickness, tunnel coefficient, and interfacial defect density. Furthermore, different charge transport mechanisms can be identified from detailed current-voltage analysis. We evaluate our characterization technique using tunnel junctions fabricated on 200 mm wafers in a complementary metal-oxide-semiconductor (CMOS)-compatible subtractive process. The results show a homogeneous average oxide thickness across the wafer with a variation below 3%. A dependence of the tunnel coefficient on oxide thickness indicates a stoichiometry gradient within the oxide. Additionally, low interfacial defect densities in the range of 70-5000 defects/cm2 are observed in our junctions, increasing with decreasing oxide thickness, suggesting that wet etching used for thickness control introduces interfacial trap states. Our study highlights the importance of advanced RT characterization for extracting tunnel junction parameters on the wafer scale, enabling effective process monitoring and optimization in industrial superconducting qubit manufacturing.

Aluminum (Al) remains the central material for superconducting qubits, and considerable effort has been devoted to optimizing its deposition and patterning for quantum devices. However, post-processing strategies focused on oxide removal of niobium (Nb) and tantalum (Ta) -based resonators using buffered oxide etch (BOE), which can not be used for Al. This challenge becomes particularly relevant for industry-scale fabrication with multi-chip bonding, where delays between sample preparation and cooldown require surface treatments that preserve low dielectric loss during extended exposure to ambient conditions. In this work, we investigate surface modification approaches for Al resonators subjected to a 24-hour delay prior to cryogenic measurement. Passivation using self-limiting oxygen and fluorine chemistries was evaluated utilizing different plasma processes. Remote oxygen plasma treatment reduced dielectric losses, in contrast to direct oxygen plasma. A fluorine-based plasma process was developed that passivated the Al surface for subsequent BOE treatment. However, the fluorine content in the surface resulted in higher loss, identifying fluorine as an unsuitable passivation material for Al resonators. Above all, selective oxide removal using HF (hydrogen fluoride) vapor and phosphoric acid yielded median dielectric losses as low as _LP = 5.7 × 10^-7 (Q_LP≈ 1.7 M) with _TLS = 3.6 × 10^-7 (Q_TLS≈ 2.8 M) in the single photon regime. Selective oxide removal provides a promising pathway for robust Al-based qubit fabrication, as it preserves low dielectric losses for a 24-hour delay before cooldown.

A novel field effect transistor concept is presented, which is suitable for chemical sensing in gases as well as in liquids. It consists of two separate components, a capacitor with a control gate and integrated chemical sensitive layer, and a metal oxide semiconductor (MOS) read-out transistor. A floating gate couples both components. The sensors are fully complementary metal-oxide-semiconductor (CMOS) compatible and have been fabricated on 200 mm silicon wafers. With identical devices, measurements of hydrogen in air and pH values in electrolytes are presented using Pd and Ta2O5 sensing layers, respectively. The preliminary experimental results demonstrate the versatility of the sensor. The possibility of detecting charge as well as capacitance variations due to chemical reactions offers new applications regarding phase change measurements and sensor calibration.

Josephson junctions (JJs) are the key element of many devices operating at cryogenic temperatures. Development of time-efficient wafer-scale JJ characterization for process optimization and control of JJ fabrication is essential. Such statistical characterization has to rely on room temperature techniques since cryogenic measurements typically used for JJs are too time consuming and unsuitable for wafer-scale characterization. In this work, we show that from room temperature capacitance and current-voltage measurements, with proper data analysis, we can independently obtain useful parameters of the JJs on wafer-scale, like oxide thickness, tunnel coefficient, and interfacial defect densities. Moreover, based on detailed analysis of current vs voltage characteristics, different charge transport mechanisms across the junctions can be distinguished. We exemplary demonstrate the worth of these methods by studying junctions fabricated on 200 mm wafers with an industrially scale-able concept based on subtractive processing using only CMOS compatible tools. From these studies, we find that our subtractive fabrication approach yields junctions with quite homogeneous average oxide thickness across the full wafers, with a spread of less then 3 variation of the tunnel coefficient with oxide thickness, pointing to a stoichiometry gradient across the junctions' oxide width. Moreover, we estimated relatively low interfacial defect densities in the range of 70 - 5000defects/cm^2 for our junctions and established that the density increased with decreasing oxide thickness, indicating that the wet etching process applied in the JJs fabrication for oxide thickness control leads to formation of interfacial trap state

Josephson junctions (JJs) are the key element of many devices operating at cryogenic temperatures. Development of time-efficient wafer-scale JJ characterization for process optimization and control of JJ fabrication is essential. Such statistical characterization has to rely on room temperature techniques since cryogenic measurements typically used for JJs are too time consuming and unsuitable for wafer-scale characterization. In this work, we show that from room temperature capacitance and current-voltage measurements, with proper data analysis, we can independently obtain useful parameters of the JJs on wafer-scale, like oxide thickness, tunnel coefficient, and interfacial defect densities. Moreover, based on detailed analysis of current vs voltage characteristics, different charge transport mechanisms across the junctions can be distinguished. We exemplary demonstrate the worth of these methods by studying junctions fabricated on 200 mm wafers with an industrially scale-able concept based on subtractive processing using only CMOS compatible tools. From these studies, we find that our subtractive fabrication approach yields junctions with quite homogeneous average oxide thickness across the full wafers, with a spread of less then 3$\,$%. The analysis also revealed a variation of the tunnel coefficient with oxide thickness, pointing to a stoichiometry gradient across the junctions' oxide width. Moreover, we estimated relatively low interfacial defect densities in the range of 70 - 5000$\,$defects/cm$^2$ for our junctions and established that the density increased with decreasing oxide thickness, indicating that the wet etching process applied in the JJs fabrication for oxide thickness control leads to formation of interfacial trap state

It will be shown that nanogaps can be fabricated by selective etching of fully strained SiGe layers embedded in single crystalline silicon. It will be shown that intrinsic stress is the dominating parameter for the anisotropy. High temperature etching with gaseous hydrochloric acid allows a large etch selectivity RSiGe/RSi depending on surface orientation, Ge concentration and temperature during etching. Multilayer nanogaps have been prepared and completely filled by several deposition techniques. Applications regarding diodes and MOSFETs will be given.

This work focuses on the manufacturing of Al/AlO x /Al Josephson junctions (JJs), which are essential components of many quantum circuits. Two processes were studied to understand the oxidation of the aluminum surface. Static oxidation was performed by removing native AlO x in a cluster system with Ar-ion beam milling and controlling the final tunneling oxide by applying a specific O 2 pressure in the chamber. Controlled plasma oxidation was performed by removing native AlO x with a H 2 plasma followed by a defined reoxidation with an oxygen plasma. The resulting oxides had thicknesses up to 10 nm and their electrical properties were analyzed on wafer level, providing insight into the structure and composition of the aluminum oxides and their applicability for Qubits. This work is crucial for reliable industrial manufacturing on full-scale 200 mm wafers with a very high uniformity level.

Nanogap technology is the basic concept for many promising devices such as localized SOI, multichannel FETs, and resonant tunneling diodes. It will be shown that intrinsic bulk strain in single crystalline silicon can be used to create homogeneous nanogaps with a few nanometer gap distance. The strain has been created by epitaxial growth of Si 1-x Ge x /Si multi-layer stacks on 200 mm (100) silicon wafers. The stacks were patterned by RIE to reveal the side walls for subsequent lateral etching with gaseous hydrochloric acid. In accordance with former investigations [1] we found that a selectivity up to 1000:1 for Si 1-x Ge x /Si can be achieved for Ge-concentrations >30% and growth temperatures T<650°C. XRD measurements, SEM pictures and wagon wheel test structures prove that for the anisotropic lateral etching behavior intrinsic strain is the dominant factor. Furthermore, the crystal orientation plays a dominant role (Fig. 1). Based on this behavior multilayer nanogaps with spacings <10 nm had been fabricated. In a subsequent process nanogaps down to 5 nm have been successfully filled completely with dielectrics and/or metals by low temperature (T<450°C) plasma oxidation, LPCVD as well as ALD (Fig. 2). The resulting nanosheets can be used for device applications. Vertical diodes and lateral MOS transistors with nanogaps and nanosheets have been fabricated. Diodes with a SiO 2 gap filling show perfect Fowler-Nordheim tunneling, which proves the high quality of the gap filling process. The electrical properties of nanogap-MOSFETs and various nanogap-diodes will be presented. [1] Destefanis et al., Semiconductor Sci. Technol. 23, 1 (2008) Fig. 1: Wagon wheel structure showing the etch anisotropy of 8 nm SiGe layer in Si Fig. 2: SEM cross section of a multistack of 6 SiGe layers selectively etched and completely filled with LPCVD oxide

For superconducting quantum circuits with a large number of Qubits, reproducible components are crucial for reducing entanglement decoherence. Particularly for reliable industrial manufacturing on full-scale 200 mm' wafers, a very high uniformity level is required to ensure sufficient coherence times. In the present work the special focus was put on manufacturing Al/AlO x /Al Josephson junctions (JJ), which are the most important component of many quantum circuit. Fully Al -based CMOS-compatible JJ’s were produced using a double dry etch process. After patterning the first Al metallization several oxidation processes have been investigated. Static oxidation has been performed by first removing the native AlOx in a multi-chamber system with Ar milling. The final tunneling oxide was controlled by applying a specific pressure in the chamber under a pure O2 atmosphere. Afterwards, without breaking the vacuum, the second Al metallization has been deposited by sputtering. Oxide thicknesses between 1 and 2.5 nm were achieved. A full mapping of the process homogeneity will be given. On the other hand, a dynamic recipe controlled plasma oxidation process was performed, where the native AlO x was first removed by a H 2 plasma followed by a defined reoxidation with an oxygen plasma. The resulting oxides had thicknesses up to 10 nm. The second Al metallization was again deposited by sputtering. Both oxidation processes were carefully studied to understand the initial oxidation process of the aluminum surface. Special attention was devoted to the non-destructive removal of the native AlOx with respect to the Al interface. Because the oxide thicknesses varied between 1 and 10 nm, the transition between direct and Fowler-Nordheim tunneling could be investigated. The process-stability on full scale 200 mm wafers and on chip size could be determined via test structures as well as the resistance variation of the Josephson junctions. Furthermore, the electrical properties of the different oxides could be measured and analyzed on wafer level. These studies provide insight into the structure and composition of the aluminum oxides and the applicability for Qubits.

Low leakage diodes are necessary in order to manufacture high-quality variable capacitance diodes (varicaps), which are used in voltage-controlled oscillators. Junction leakage current affects the single sideband noise of the oscillator by up-conversion of 1/ f and shot noise (Chan et al. in IEEE Trans Electron Devices 54(9):2570–2573, 2007, https://doi.org/10.1109/TED.2007.903201 ). Several sources show higher leakage current for RTP compared to furnace anneal (Lunnon et al. in J Electrochem Soc 132(10):2473, 1985, https://doi.org/10.1149/1.2113602 , Gramenova et al. in J Electrochem Soc 146(1):359, 1999, https://doi.org/10.1149/1.1391613 , Mikoshiba et al. in Jpn J Appl Phys, 1986, https://doi.org/10.1143/jjap.25.l631 ). In our experiments, we found lower leakage currents for RTP compared to furnace annealing. We present results from annealing experiments where we compare three annealing conditions with and without oxidizing annealing conditions. Graphical abstract

Abstract. Background: Physical modeling of grayscale lithography processes for the prediction of photoresist heights leads to complex mathematical algorithms. A promiment example is the numerical simulation of the photoresist shape after development through Dill’s equations. These grayscale lithography models exhibit accurate prediction quality but can not directly implemented into mask layout tools to simplify the layout procedure. Limited process windows, changes in the mask design, variations of the used materials or manufacturing tools lead to time-consuming and cost-intensive test procedures to adjust the photoresist model for sufficient results. Aim: The focus of this work is to enhance current grayscale lithography models for a straightforward method with the same precise prediction of remaining photoresist heights to simplify the mask layout process. Moreover, we aim for an uncomplicated optimization of the model to minimize the empirical analysis necessary for its use. Approach: Based on experimental results, we deploy a sectionally defined mathematical expression that includes the theory of Fraunhofer diffraction and illumination-dependent activation of the photo-sensitive component and its solubility in developer. Results: We produced pyramidal, spherical and chess field structures with exposure doses of 3000 and 15  ,  000  J  /  m2 on bare silicon substrates with 100-nm resolution and on silicon substrates with anti-reflective coatings, with accuracy as fine as 20 nm. Conclusion: The proposed three-state lithography model has been verified by experimental evaluation. It is able to operate in a wide process window and can be directly implemented in existing mask layout software. This model ensures a cost-efficient and precisely controlled production of three-dimensional topographies using grayscale lithography processes.

An argon/hydrogen discharge plasma was created with a UHV compatible plasma source. This low energy plasma was utilized to remove - in a single step - the native oxide and the hydro- carbons from the wafer surface at substrate temperatures be- tween 100°C and 400°C. During the plasma cleaning procedure, residual gas ions were monitored to elucidate the process chem- istry. To optimize the procedure, the interfaces between the plasma cleaned wafer and the MBE grown epilayer were investi- gated by scanning electron microscopy (SEM) and cross-sectional transmission electron microscopy (XTEM). The cleaning process was also applied to patterned silicon substrates. Subsequent local epitaxial growth by MBE at 550°C without the typical high temperature annealing step was achieved, suggesting that the in-situ dry cleaning procedure caused no surface damage.

Unannealed neutron transmutation doped silicon substrates with a target resistivity of approximately 1000Ωcm are characterized for radiation induced defects by means of microwave detected photoinduced current transient spectroscopy (MD-PICTS). This technique is a contactless advancement of conventional PICTS and does not require the fabrication of ohmic contacts. Defect spectroscopy by means of MD-PICTS is conducted in a broad temperature range between 30 K and 293 K, which makes it possible to identify energetically shallow as well as deep traps. In addition, a wavelength dependent analysis is performed to determine whether a defect is located at the surface or in the bulk material. Three traps with an average activation energy of 68meV, 85meV, and 150meV are observed. In addition, an indication for deep defect states with activation energies between 320meV and 480meV is found. According to the wavelength dependent analysis, it is assumed that all observed traps are bulk defects. Finally, a minority carrier lifetime of approximately 0.7 μs is determined, suggesting that the crystal is heavily damaged by neutron radiation.

Hybrid materials based on inorganic particles and an organic polymer were developed and used as an efficient sensing material for carbon dioxide (CO2). The sensing material consists of fumed silica that is functionalized with an organic polymer, polyethylenimine, by means of the impregnation method. The organic polymer is effectively immobilized around the silica nanoparticles and confirmed by infrared spectroscopy. Thermogravimetric analysis proves the thermal stability of the sensing material. CO2 capacitive sensors operating at temperatures lower than 70 °C were fabricated by depositing a thin layer of hybrid sensing material on interdigitated gold electrodes. Impedance spectroscopy explored the sensing capability of the hybrid organic–inorganic material towards CO2 in the presence of different relative humidity levels, as well as its stability and reversibility. This strategy to couple organic and inorganic materials as a sensing layer for CO2 paves the way for the design of a low-cost CO2 sensor.

Contactless minority carrier lifetime (lifetime) measurements by means of microwave detected photoconductivity are employed for oxidation process characterization and furnace profiling. Characterization is performed on oxidized float zone substrates with high resistivity and outstanding bulk quality, suggesting that the measured effective lifetime is strongly dominated by interface recombination and therefore reflects the oxide quality. The applied approach requires neither test structures nor time consuming measurements and is therefore of particular interest if high throughput is required. The method is used to investigate the impact of oxidation furnace leakage as well as to analyze the oxidation homogeneity across a horizontal oxidation furnace. For comparison, capacitance-voltage measurements are conducted to characterize the oxide properties. It is found that any type of furnace leakage, which induces fixed oxide charges as well as interface states, has a heavy impact on the measured effective lifetime, especially on the shape of generation rate dependent lifetime curves. Furthermore, a distinct lifetime decrease towards the tube door of the oxidation furnace could be observed. The latter is even detectable in an ideal oxidation process, generating high quality oxides. Besides plain equipment characterization, the presented approach is suitable to optimize the oxidation process itself regarding different parameters like temperature, gas flow, pressure, or process time.

A low power, network-ready demonstrator for sensing carbon dioxide, humidity and temperature simultaneously is designed.Contrary to conventional NDIR systems, the is based on a capacitive readout of an interdigitated transducer coated with polymeric sensing materials sensitive to CO2 and humidity, respectively.A microcontroller is used to control the optimum working temperature of the sensor.The capacitance is measured based on the charge transfer capacitance measuring circuit.A restricted number of components is employed to meet low-cost and low power requirements.The system is tested in an office environment and compared to commercially available systems.It exhibits excellent results and is suited for an integration in automated HVAC systems.

The development of humidity sensors with simple transduction principles attracts considerable interest by both scientific researchers and industrial companies.Capacitive humidity sensors, based on polyimide sensing material with different thickness and surface morphologies, are prepared.The surface morphology of the sensing layer is varied from flat to rough and then to nanostructure called nanograss by using an oxygen plasma etch process.The relative humidity (RH) sensor selectively responds to the presence of water vapor by a capacitance change.The interaction between polyimide and water molecules is studied by FTIR spectroscopy.The complete characterization of the prepared capacitive humidity sensor performance is realized using a gas mixing setup and an evaluation kit.A linear correlation is found between the measured capacitance and the RH level in the range of 5 to 85%.The morphology of the humidity sensing layer is revealed as an important parameter influencing the sensor performance.It is proved that a nanograss-like structure is the most effective for detecting RH, due to its rapid response and recovery times, which are comparable to or even better than the ones of commercial polymer-based sensors.This work demonstrates the readiness of the developed RH sensor technology for industrialization.

The gases used in industrial cleaning processes are considered greenhouse gases with a high global warming potential (GWP). It is important to provide a viable alternative chemical vapor deposition (CVD) cleaning gas that is capable of removing efficiently deposited layers on the CVD chamber inner wall and other parts of the apparatus. The cleaning gas has to be environmental friendly in order to avoid accentuation of the global warming phenomena. Besides that, the alternative cleaning gas should be compatible with the existing gas delivery system and the CVD equipment that is already used by industrial companies. Only by fulfilling the three requirements mentioned above is it possible to replace the well-established cleaning gases. In this project, an F2–gas mixture for the in-situ cleaning of CVD chambers has been studied and compared with conventional cleaning methods. The conventional cleaning process is defined as a cleaning procedure using either C2F6 in RF plasma discharge or NF3 in remote plasma discharge.

A new field-effect transistor based transducer concept is presented, for measuring both, liquid and gaseous media. It uses a Faraday cup with a floating electrode inside, which is connected to the gate of a MOS like transistor. The SOI based technological realization allows a new degree of freedom for more flexible measurements as compared to conventional FET based transducers. Potentiometric measurements are presented. Additionally the SOI technology allows simple packaging.