A new silicon solar cell structure is presented in which the p–n junction is formed by alloying aluminum with n-type silicon, and where this p–n junction is located at the back (unilluminated) side of the cell. With a phosphorus front diffusion, the resultant n+np+ structure has been implemented using dendritic web silicon substrates which are 100μm thick and doped with antimony to 20Ωcm. Such a structure eliminates shunting of the p–n junction, provides an effective front surface field, enables a high minority carrier lifetime in the base, and is immune to light-induced degradation. Using only production-worthy, high-throughput processes, aluminum alloy back junction dendritic web cells have been fabricated with efficiencies up to 14.2% and with corresponding minority carrier (hole) lifetime in the base of 115μs.

A comprehensive and systematic investigation of low-cost surface passivation technologies is presented for achieving high-performance silicon devices such as solar cells. Most commercial solar cells today lack adequate surface passivation, while laboratory cells use conventional furnace oxides (CFO) for high-quality surface passivation involving an expensive and lengthy high-temperature step. This investigation tries to bridge the gap between commercial and laboratory cells by providing fast, low-cost methods for effective surface passivation. This paper demonstrates for the first time, the efficacy of TiO2, thin (<10 nm) rapid thermal oxide (RTO), and PECVD SIN individually and in combination for (phosphorus diffused) emitter and (undiffused) back surface passivation. The effects of emitter sheet resistance, surface texture, and three different SIN depositions (two direct PECVD systems and one remote plasma system) were investigated. The effects of post-growth/deposition treatments such as forming gas anneal (FGA) and firing of screen-printed contacts were also examined. This study reveals that the optimum passivation scheme consisting of a thin RTO with a SiN cap followed by a very short 730 degrees C anneal can 1) reduce the emitter saturation current density, J(0e), by a factor of >15 for a 90 Omega/sq emitter, 2) reduce J0(e) by a factor of >3 for a 40 Omega/sq emitter, and 3) reduce S-back below 20 cm/s on 1.3 Omega p-Si. Furthermore, this double-layer RTO+SiN passivation is relatively independent of the deposition conditions (direct or remote) of the SiN film and is more stable under heat treatment than SiN or RTO alone. Model calculations are also performed to show that the RTO+SiN surface passivation scheme may lead to 17%-efficient thin screen-printed cells even with a low bulk lifetime of 20 mu S.

The overall objectives of this program are (1) to develop rapid and low-cost processes for manufacturing that can improve yield, throughput, and performance of silicon photovoltaic devices, (2) to design and fabricate high-efficiency solar cells on promising low-cost materials, and (3) to improve the fundamental understanding of advanced photovoltaic devices. Several rapid and potentially low-cost technologies are described in this report that were developed and applied toward the fabrication of high-efficiency silicon solar cells.

Rapid and potentially low-cost processing techniques are analyzed and applied toward the fabrication of high-efficiency Si solar cells. (i) A technology that can simultaneously form the phosphorus emitter, boron BSF, and in situ oxide in a single high-temperature furnace step or: simultaneously diffused, textured, and AR coated process (STAR) is presented. (ii) A high quality screen-printed (SP) contact methodology is developed that results in fill factors of 0·785–0·790 on monocrystalline Si. (iii) Aluminum back surface field (Al-BSF) formation is studied in detail to establish the process conditions that result in optimal BSF action. (iv) Screen-printing of Al conductor paste and rapid thermal processing (RTP) are integrated into the BSF procedure, and effective recombination velocities ( S eff ) as low as 200 cm/s are demonstrated on 2·3 Ω-cm Si with this rapid thermal processing of screen-printed contacts, Al alloyed BSF processes. (v) A novel passivation scheme consisting of a dielectric stack (plasma silicon nitride on top of a rapid thermal oxide) is developed to reduce the surface recombination velocity ( S ) to ≈ 10 cm/s at the 1·3 Ω-cm Si surface. The important feature of this stack passivation scheme is its ability to withstand a high-temperature anneal (700–850°C) without degradation in surface recombination velocity. This feature is critical for most current commercial processes that utilize SP contact firing. (vi) Finally, the individual processes are integrated to form high-efficiency, manufacturable devices. Solar cell efficiencies of 17% and >19% are achieved on FZ Si with SP and evaporated (photolithography) contacts, respectively.

Rapid and potentially low-cost process techniques are analyzed and successfully applied toward the fabrication of high-efficiency monocrystalline Si solar cells. First, a methodology for achieving high-quality screen-printed (SP) contacts is developed to achieve fill factors (FF's) of 0.785-0.795 on monocrystalline Si. Second, rapid emitter formation is accomplished by diffusion under tungsten halogen lamps in both beltline and rapid thermal processing (RTP) systems (instead of in a conventional infrared furnace). Third, a combination of SP aluminum and RTP is used to form an excellent back surface field (BSF) in 2 min to achieve an effective back surface recombination velocity (S/sub eff/) of 200 cm/s on 2.3 /spl Omega/-cm Si. Next, a novel dielectric passivation scheme (formed by stacking a plasma silicon nitride film on top of a rapid thermal oxide layer) is developed that reduces the surface recombination velocity (S) to approximately 10 cm/s on the 1.3 /spl Omega/-cm p-Si surface. The essential feature of the stack passivation scheme is its ability to withstand short 700-850/spl deg/C anneal treatments (like the ones used to fire SP contacts) without degradation in S. The stack also lowers the emitter saturation current density (J/sub oe/) of 40 and 90 /spl Omega//sq emitters by a factor of three and ten, respectively, compared to no passivation. Finally, the above individual processes are integrated to achieve (1) >19% efficient solar cells with emitter and Al-BSF formed by RTP and contacts formed by vacuum evaporation and lift-off, (2) 17% efficient manufacturable cells with emitter and Al-BSF formed in a beltline furnace and contacts formed by SP, and (3) 17% efficient gridded-back contact (bifacial) cells with surface passivation accomplished by the stack and gridded front and back contacts formed by SP and cofiring.

A detailed comparison of the passivation quality and its dependence on the low and high temperature anneals is presented for various promising Si surface passivation schemes. The passivation schemes investigated in this study include: conventional furnace oxide (CFO), rapid thermal oxide (RTO), belt line oxide (BLO), plasma deposited oxide (PDO), SiN deposited by plasma enhanced chemical vapor deposition (PECVD), CFO/SiN, RTO/SiN, BLO/SiN, PDO/SiN, and RTO/PDO. Passivated low resistivity (1 Ohm cm) p-type silicon samples were subjected to three annealing treatments: (a) 400 degrees C in forming gas (FGA), (b) 730 degrees C in air, and (c) 850 degrees C in air, to simulate heat-treatments, which are typically used for contact anneal, front ohmic contacts, and back surface field formation, respectively, for screen printed silicon solar cells. It is found that the passivation quality of PDO, SiN, RTO, and CFO single layers improves significantly after the 400 degrees C FGA and 730 degrees C thermal cycles with RTO resulting in the lowest surface recombination velocities (S-eff) of 154 and 405 cm/s, respectively. Silicon wafers coated with belt oxide (BLO and BLO/SiN) did not show any improvement in S-eff, which remained at 5000 cm/s due to the inferior quality of BLO formed in compressed air. The oxide/ nitride stack passivation is found to be far superior to single-layer passivation resulting in S-eff Of 70 cm/s for the RTO/SiN scheme after the two high temperature anneals (850 and 730 degrees C). The hydrogen concentration measurements by Fourier transform infrared spectroscopy show a greater decrease in the hydrogen content in the annealed RTO/SiN stack compared to the as-deposited SiN single layer after the 730 and 850 degrees C anneals. A combination of reduced hydrogen content and very low S-eff in the RTO/SiN stack suggests that the release of hydrogen from SiN during the anneal further passivates the RTO/Si interface underneath. (C) 1999 The Electrochemical Society. S0013-4651(98)08-117-8. All rights reserved.

Rapid and potentially low-cost process techniques are analyzed and applied toward the fabrication of high-efficiency Si solar cells. First, a high quality screen-printed (SP) contact methodology is developed that results in fill factors of 0.785-0.790 on monocrystalline Si. Nest, aluminum back surface field (Al-BSF) formation is studied in detail to establish the process conditions that result in optimal BSF action. Screen-printing of Al conductor paste and rapid thermal processing (RTP) are integrated into the BSF procedure, and effective recombination velocities (S-eff) as low as 200 cm/s are demonstrated on 2.3 Omega-cm Si with this RTP SP Al-BSF process. A novel passivation scheme consisting of a dielectric stack (plasma silicon nitride on top of a rapid thermal oxide) is developed to reduce the surface recombination velocity (S) to approximate to 10 cm/s at the 1.3 Omega-cm Si surface. The important feature of this stack passivation scheme is its ability to withstand a high-temperature anneal (700-850 degrees C) without degradation in S. This feature is critical for most current commercial processes that utilize SP contact firing. Finally, the individual processes are integrated to form high-efficiency, manufacturable devices. Solar cell efficiencies of 17% and >19% are achieved on FZ Si with SP and evaporated (photolithography) contacts, respectively.

Presented at the 2nd World Conference on Photovoltaic Solar Energy Conversion; Vienna, Austria; July 6-10, 1998.

For the first time, cells formed hy rapid thermal processing (RTP) have resulted in 18%-efficient 1 and 4 cm(2) single-crystal silicon solar cells. Front surface passivation by rapid thermal oxidation (RTO) significantly enhanced the short wavelength response and decreased the effective front surface recombination velocity (including contact effects) from 7.5 x 10(5) to about 2 x 10(4) cm/s, This improvement resulted in an increase of about 1% (absolute) in energy conversion efficiency, up to 20 mV in V(oc), and about 1 mA/cm(2) in J(sc). These RTO-induced enhancements are shown to be consistent with model calculations. Since only 3 to 4 min are required to simultaneously form the phosphorus emitter and aluminum back-surface-field (BSF) and,5 to 6 min are required for growing the RTO, this RTP/RTO process represents the fastest technology for diffusing and oxidizing greater than or equal to 18%-efficient solar cells. Both cycles incorporate an in situ anneal lasting about 1.5 min to preserve the minority carrier lifetime of lower quality materials such as dendritic-web and multicrystalline silicon. These high-efficiency cells confirmed that RTP results in equivalent performance to cells fabricated by conventional furnace processing (CFP), Detailed characterization and modeling reveals that because of RTO passivation of the front surface (which reduced J(oe),, by nearly a factor of ten), these RTP/RTO cells have become base dominated ( J(ob) much greater than J(oe)), and further improvement in cell efficiency is possible by a reduction in back surface recombination velocity (BSRV), Based upon model calculations, decreasing the BSRV to 200 cm/s is expected to give 20%-efficient RTP/RTO cells.

This paper presents, for the first time, the successful integration of three rapid, low-cost, high-throughput technologies for silicon solar cell fabrication, namely: rapid thermal processing (RTP) for simultaneous diffusion of a phosphorus emitter and aluminum back surface field; screen printing (SP) for the front grid contact; and low-temperature plasma-enhanced chemical vapor deposition (PECVD)...

Crystalline silicon is the dominant photovoltaic (PV) material today. Although laboratory cell efficiencies have reached 24%, production cell efficiencies are still in the range of 11-15% at a market price of $4/watt for modules. The real challenge is how to incorporate high efficiency features in the industrial cells in a cost-effective manner. This paper highlights the key high efficiency attributes that can bridge the gap between laboratory and industrial cells. It summarizes some of the recent developments and emerging technologies that have the potential of reaching the cost and efficiency targets simultaneously. Further development of these technologies, along with the push to increase the market size towards 500 MW/yr can lead to next generation silicon cells that can reduce the silicon PV module cost down to $1-2/watt.

We have optimized plasma-enhanced chemical vapor deposition (PECVD) of SiN-based antireflection (AR) coatings with special consideration for the short-wavelength (<600 nm) parasitic absorption in SiN. Spectroscopic ellipsometry was used to measure the dispersion relation for both the refractive index n and the extinction coefficient k, allowing a precise analysis of the trade-off between reflection and absorption in SiN-based AR coatings. Although we focus on photovoltaic applications, this study may be useful for photodetectors, IR optics, and any device for which it is essential to maximize the transmission of light into silicon. We designed and optimized various AR coatings for minimal average (spectrally) weighted reflectance (? R(w) ?) and average weighted absorptance (? A (w) ?), using the air mass 1.5 global solar spectrum. In most situations ? R (w) ? decreased with higher n, but ? A (w) ? increased because k increased with n. For the practical case of a single-layer AR coating for silicon under glass, an optimum refractive index of ~2.23 (at 632.8 nm) was determined. Further simulations revealed that a double-layer SiN stack with an n = 2.42 film underneath an n = 2.03 film gives the minimum total photocurrent loss. Similar optimization of double-layer SiN/SiO(2) coatings for silicon in air revealed an optimum of n = 2.28 for SiN. To determine the allowable tolerance in index and film thickness, we generated isotransmittance plots, which revealed more leeway for n values below the optimum than above because absorption begins to reduce photocurrent for high n values.

This paper presents, for the first time, the successful integration of three rapid, low-cost, high-throughput techniques for crystalline Si cell fabrication, namely: rapid thermal processing (RTP) for simultaneous diffusion of a phosphorus emitter and aluminum back-surface-field; screen-printing (SP) for the front grid contact; and low-temperature PECVD of SiN for antireflection and surface passivation. This combination has resulted in 4 cm/sup 2/ cells with efficiencies of 16.3% and 15.9% on 2 /spl Omega/-cm FZ and Cz, respectively, as well as 15.4% efficient, 25 cm/sup 2/ FZ cells. Despite the respectable RTP/SP efficiencies, cells formed by conventional furnace processing and photolithography (CFP/PL) give /spl sim/2% (abs.) greater efficiencies. Through in-depth modeling and characterization, this difference is quantified on the basis of emitter design, grid shading, and quality of contacts.

A detailed investigation of quality enhancement techniques, such as plasma enhanced chemical vapor deposition (PECVD) of SiO2/SiN coating, forming gas anneal (FGA) and Al gettering was conducted to improve the performance of cells fabricated on several promising multicrystalline silicon (mcs) materials. A large amount of hydrogen and positive charge in the PECVD SiN antireflection (AR) coating play an important role in passivating surface and bulk defects in silicon. Appropriate post‐PECVD deposition anneal was found to be important in maximizing the benefit from PECVD AR coating. Low temperature anneal at 350 °C/20 min improves the short wavelength response due to surface passivation along with some increase in the long wavelength response due to bulk defect passivation in certain mcs materials. Post‐PECVD rapid thermal anneals (RTA) in the range of 350 to 750 °C significantly improve the long wavelength response of certain materials such as EFG silicon. However, this comes at the expense of short wavelength response due to increased absorption in the SiN film. Electron beam induced current (EBIC) measurements revealed significant increase in the intragrain response of these cells after post‐PECVD anneal. Al gettering of mcs showed a significant improvement in bulk lifetime and cell efficiency. Forming gas anneal, after phosphorus and Al diffusions, resulted in additional improvements in bulk lifetime in certain materials due to hydrogen passivation. Cells fabricated on cast mcs from Osaka Titanium Corporation (OTC) and Crystal Systems gave cell efficiencies in the range of 17 to 18%. Without the appropriate gettering and passivation techniques these materials give cell efficiencies in the range of 14.5 to 15.5%.

Solar cells with efficiencies as high as 18.6% (1 cm2 area) have been achieved by a process which involves impurity gettering and effective back surface passivation on 0.65 Ω-cm multicrystalline silicon (mc-Si) grown by the heat exchanger method (HEM). This represents the highest reported solar cell efficiency on mc-Si to date. PCD analysis revealed that the bulk lifetime (τb ) in HEM samples after phosphorus gettering can be as high as 135 μs. This increases the impact of the back surface recombination velocity (Sb) on the solar cell performance. By incorporating a deeper aluminum BSF, the Sb for solar cells in this study was lowered from 10000 cm/s to 2000 cm/s on HEM mc-Si. This combination of high τb and moderately low Sb resulted in the record high efficiency mc-Si solar cell. Model calculations indicate that lowering Sb further can raise the efficiency of untextured HEM mc-Si solar cells above 19.0%, thus closing the efficiency gap between good quality, untextured single crystal and mc-Si solar cells

For the first time, the potentially cost-effective technologies of rapid thermal processing (RTP) and screen-printing (SP) have been combined into a single process sequence to achieve solar cell efficiencies as high as 14.7% on 0.2 Omega-cm FZ and 14.8% on 3 Omega-cm Ct silicon. These results were achieved without application of a nonhomogeneous (selective) emitter, texturing, or oxide passivation, By tailoring the RTP thermal cycles for emitter diffusion and firing of the screen-printed silver contacts, fill factor values >0.79 were realized on emitters with a sheet resistance (rho(s)) of similar to 20 Omega/square and grid shading <6%, Such high fill factors clearly demonstrate that screen-printed contacts can be fired on extremely shallow RTP emitters (x(j) = 0.25 - 0.3 mu m) without shunting cells, IQE analysis depicts a strong preference for shallow emitter junction depths to achieve optimal short wavelength response of these unpassivated emitters, In some cases, front contacts were printed through plasma enhanced chemical vapor deposited (PECVD) SiN/SiO2 dielectrics which prevented the shunting of shallow emitters by serving as partial barriers minimizing the diffusion of metallic species from the contacts. The firing of screen-printed contacts through these PECVD films, achieved the multiple purposes of contact formation, efficient front surface passivation due to annealing of the SW, and high quality antireflection (AR), Research is presently underway to further optimize the RTP emitter design for screen-printing and develop techniques for implementing selective emitter and oxide passivation technologies for higher efficiency cells.

Plasma enhanced chemical vapor deposition (PECVD) passivation of bulk and surface defects has been shown to be an important technique to improve the performance of multicrystalline silicon (mc-Si) and single crystalline silicon solar cells. In this paper, we report the status of our on-going investigation into the bulk and surface passivation properties of PECVD insulators for photovoltaic applications. The objective of this paper is to demonstrate the ability of PECVD films to passivate the front (emitter) surface, bulk, and back surface by proper tailoring of deposition and post-PECVD annealing conditions.

Silicon solar cell efficiencies of 16.9% have been achieved on 0.2 Ω cm float zone silicon, using a simplified cost effective rapid thermal process (RTP). Although the individual processing steps are not fully optimized yet, this represents the highest reported efficiency for solar cells processed with simultaneous front and back diffusion with no conventional high-temperature furnace steps. A diffusion temperature schedule coupled with an added short in situ slow cooling during RTP resulted in greater than 200 μm diffusion length and appropriate diffusion profiles for high efficiency cells. Plasma enhanced chemical vapor deposition (PECVD) of SiN/SiO2 was used for surface passivation and antireflection coating. Conventional cells fabricated by furnace diffusions and oxidations gave an efficiency of 18.8%. Process optimization can further reduce the gap between the conventional and RTP/PECVD cells.

Silicon solar cell efficiencies of 17.1%, 16.4%, 14.8%, and 14.9% have been achieved on FZ, Cz, multicrystalline (mc-Si), and dendritic web (DW) silicon, respectively, using simplified, cost-effective rapid thermal processing (RTP). These represent the highest reported efficiencies for solar cells processed with simultaneous front and back diffusion with no conventional high-temperature furnace steps. Appropriate diffusion temperature coupled with the added in-situ anneal resulted in suitable minority-carrier lifetime and diffusion profiles for high-efficiency cells. The cooling rate associated with the in-situ anneal can improve the lifetime and lower the reverse saturation current density (Jo), however, this effect is material and base resistivity specific. PECVD antireflection (AR) coatings provided low reflectance and efficient front surface and bulk defect passivation. Conventional cells fabricated on FZ silicon by furnace diffusions and oxidations gave an efficiency of 18.8% due to greater short wavelength response and lower Jo