Algorithms for collision search in finite sets are a key tool for security assessment of modern real world crypto-systems. Two notable applications of collision search are the Pollard rho algorithm to solve the elliptic curve discrete logarithm problem (ECDLP) and the birthday search for finding collisions of cryptographic hash functions like MD5 and SHA1. The ability to design and implement efficient hardware architectures for such algorithms can have a significant impact on the practical security of a variety of crypto-systems submitted in the real world.We present a general many-core architecture and an optimization methodology thereof, for cryptanalytic collision search on Field Programmable Gate Arrays (FPGAs). We use such architecture for two relevant case studies, i.e., (i) the Pollard rho algorithm to solve the ECDLP for security assessment of elliptic curve cryptography (ECC), and (ii) the birthday search algorithm to find chosen-prefix collisions for security assessment of the MD5 cryptographic hash function.

Nowadays, many services and applications need to be secured. In this paper we present the design and the initial development of a new security-oriented open hardware and software platform easy to be integrated and capable of hiding significant complexity behind a set of simple high-level APIs. This SoC platform is called SEcube™ (Secure Environment cube). It is a single-chip design that embeds three main cores: a highly powerful processor, a Common Criteria certified smartcard, and a flexible FPGA. The SEcube™ platform provides several functional entry levels, ranging from the hardware to software APIs amenable to become service-ready in a near future. This way, developers who do not feel comfortable on security aspects can use the easy-to-use API abstraction layer and experience the Cube as a high-security black box. Conversely, security experts can avail of the open source character, and verify, change, or write from scratch the entire system, starting from the elementary low-level blocks.

To be understandable and reusable at large scale, also by non-experts in security, Crypto primitives must be implemented in a modular way, and come with well organized and well described processes to help understanding, foster adoption, and ensure a proper embedding in the applications they must protect. In this paper, we reap the benefits of the modular hardware and software architecture of the SEcube, and lift the issue of crypto-primitives management from the traditional code level to a model driven approach. On small examples, we illustrate the essential features of the approach concerning the modelling of cryptography primitives as SIBs and their organization in domain-specific SIB palettes. We also sketch how to use multifaceted taxonomies to provide compact yet expressive classifications, amounting to a semantic description of the security domain. We address in the issue of workflows by using models that ease the expression, analysis, control, and formal verification of inter- and intra-model control and data flow, though the adoption of the XMDD approach implemented in the DIME integrated modelling environment. A brief description of a home banking application sketches how in reality many of these security mechanisms need to work together in a safe and secure orchestration.

Current trends for ubiquitous data usage have made information security as a mandatory component of any system. The availability of su itable levels of protection for data is required to secure any kind of content throughout its lifecycle and independently from the media, which allows the data to be used. In this paper we present a methodology to provide data protection through a simple and effective security abstraction layer based on the SEcube™ (Secure Environment cube) single chip, a new security-oriented open hardware and software platform . After analyzing the most critical information states, we introduce a set of easy-to-use APIs that provide an open-sour ce, multi-paradigm security layer, suitable to protect both dat a at rest and data in motion. Being the SEcube™ made up of three hardware elements (a highly powerful processor, a Common Criteria certified smartcard and a flexible FPGA) , all the functions are implemented and executed in a fully controlled secure environment. All the complexities related to key management and algorithms are handled within the secure environment, leaving the developers free to focus on the final applications and services.

The presence of noise in images can significantly impact the performances of digital image processing and computer vision algorithms. Thus, it should be removed to improve the robustness of the entire processing flow. The noise estimation in an image is also a key factor, since, to be more effective, algorithms and denoising filters should be tuned to the actual level of noise. Moreover, the complexity of these algorithms brings a new challenge in real-time image processing applications, requiring high computing capacity. In this context, hardware acceleration is crucial, and Field Programmable Gate Arrays (FPGAs) best fit the growing demand of computational capabilities. This paper presents an Adaptive Image Denoising IP-core (AIDI) for realtime applications. The core first estimates the level of noise in the input image, then applies an adaptive Gaussian smoothing filter to remove the estimated noise. The filtering parameters are computed on-the-fly, adapting them to the level of noise in the image, and pixel by pixel, to preserve image information (e.g., edges or corners). The FPGA-based architecture is presented, highlighting its improvements w.r.t. a standard static filtering approach.

Thanks to their flexibility, increasing performances and low Non-Recurrent Engineering costs, SRAM-based Field Programmable Gate Array (FPGA) devices often represent the preferred platforms for the final deployment of highly reliable systems. In this context, Dynamic Partial Reconfiguration (DPR) is far from being widely adopted due to the additional complexity introduced during the hardware design phase, and the dependability issues related to the FPGA reconfiguration process itself. This paper presents a portable open-source controller for safely enabling self dynamic and partial reconfiguration of systems implemented on Xilinx FPGAs. The controller embeds configurable error detection and correction circuitry that enables a safe DPR by monitoring for partial bitstreams data errors. Experiments highlight the high performances achieved and the limited hardware resources needed to implement it on different devices. The HDL source code has been made available through the popular open-source Cobham Gaisler GRLIB IP-cores library.

Elliptic Curve Cryptography (ECC) is a popular tool to construct public-key crypto-systems. The security of ECC is based on the hardness of the elliptic curve discrete logarithm problem (ECDLP). Implementing and analyzing the performance of the best known methods to solve the ECDLP is useful to assess the security of ECC and choose security parameters in practice. We present a novel many-core hardware architecture implementing the parallel version of Pollard’s rho algorithm to solve the ECDLP. This architecture results in a speed-up of almost 300% compared to the state of the art and we use it to estimate the monetary cost of solving the Certicom ECCp-131 challenge using FPGAs.

Dependability issues due to nonfunctional properties are emerging as a major cause of faults in modern digital systems. Effective countermeasures have to be developed to properly manage their critical timing effects. This article presents a methodology to avoid transition delay faults in field-programmable gate array (FPGA)-based systems, with low area overhead. The approach is able to exploit temperature information and aging characteristics to minimize the cost in terms of performances degradation and power consumption. The architecture of a hardware manager able to avoid delay faults is presented and analyzed extensively, as well as its integration in the standard implementation design flow.

Cobham Gaisler develops the LEON3FT SPARC V8 fault-tolerant microprocessor that is available both as IP cores part of an IP library (GRLIB) that allows users to design their own custom system-on-chip (SoC) designs, and also as part of ready-made designs and devices. Cobham Gaisler has recently added support for Microsemi IGLOO2, and experimental support for Microsemi radiation-tolerant RTG4, devices to GRLIB. The presentation will give an overview of LEON processor system-on-chip architectures that are currently supported for the latest generation Microsemi devices and will provide an overview of the steps and obstacles in porting existing IP cores to these devices.

High computation is a predominant requirement in many applications. In this field, Graphic Processing Units (GPUs) are more and more adopted. Low prices and high parallelism let GPUs be attractive, even in safety critical applications. Nonetheless, new methodologies must be studied and developed to increase the dependability of GPUs. This paper presents an improved fault mitigation strategy against permanent faults for CUDA Fermi GPUs. The proposed approach exploits the reverse engineering of the block scheduling policy in CUDA Fermi GPUs in order to minimize the fault mitigation timing overhead. The graceful performance degradation achieved by the proposed technique outperforms multithreaded CPU implementations and other fault mitigation strategies for CUDA GPU, even in presence of multiple permanent faults

Camera shake is a well-known source of degradation in digital images, as it introduces motion blur. Taking satisfactory photos under dim lighting conditions or using a hand-held camera is challenging. Same problems arise when camera is connected to mechanical equipments, that transfer vibrations to the camera itself. Since decades, many different theories and algorithms have been proposed with the aim of retrieving latent images from blurry inputs; most of them work quite well, but very often incur in large execution times. There are cases in which images have to be analyzed looking for features to be extracted; in this cases, it may be useful to consider deblurring as a pre-processing stage, that should not affect the performances of the whole image processing architecture, in terms of throughput. In this paper, an extensive survey of the deblurring algorithms that have been developed during the last 40 years is provided. Aim of this paper is to highlight software approaches that are able to quickly process input images and obtain good quality outcomes, analyzing the possibility of an hardware implementation to meet real-time requirements.

I. POSTER ABSTRACT Nowadays, space agencies have increased their research efforts in order to enhance the success rate of space exploration missions. The guided landing is becoming an hot topic and future space missions will increasingly adopt Video Based Navigation (VBN) systems to assist the entry, descent and landing (EDL) phase of space modules, enhancing the precision of automatic EDL systems. Video-based navigation (VBN) is a well-studied area of computer vision spanning several application fields, including robotics, unmanned vehicles, and avionics. VBN is also gaining importance in space applications where Image Processing (IP) is becoming more and more important to enhance the on-board advanced avionics functionalities. Different mission types will benefit of the IP outputs to increase the reliability and the accuracy of the navigation system. Typical applications are RdV, Debris Removal, In Orbit Servicing, Rovers/Robots and Descent & Landing on planets. As example, for in orbit operations the identification and the relative position determination of the target from images are essential for supporting the docking or capture of collaborative and in particular non-collaborative objects. Instead, for Rovers and Robots, vision is necessary to support the reconstruction of the terrain maps, the determination of the safe path planning, and the identification of scientific targets. For Descent and Landing on remote planets, where the autonomy is a critical factor, cameras have already been used on past missions but with limited on board capabilities, whereas IP is deemed a key feature to be integrated in the GNC in order to improve the reliability and precision (in particular during the absolute/relative navigation and hazard mapping/avoidance). The usage of a VBN system will allow to design an autonomously guided EDL system able not only to reduce the landing ellipse, but also to avoid the landing in dangerous area of the planet surface (e.g., huge craters or big stones), that could lead to the mission failure. A VBN system executes very computationally intensive image processing algorithms. Since real-time performances are mandatory, it must be able to compute these algorithms at high speed. A software implementation of the complete image processing chain cannot reach the required performances, thus the emerging trend is to accelerate portions of the image processing algorithms via hardware. In space-applications, Field Programmable Gate Arrays (FPGAs) are increasingly replacing Application Specific Integrated Circuits (ASICs). They are highly versatile, featuring dedicated carry structures to support adders, accumulators and counters, and offer cheaper cost per …

Modern SRAM-based Field Programmable Gate Arrays (FPGAs) are increasingly employed in safety- and mission-critical applications. However, the aggressive technology scaling is highlighting the increasing sensitivity of such devices to Single Event Upsets (SEUs) caused by external radiation events. Assessing the reliability of FPGA-based systems in the early design stages is of upmost importance, allowing design exploration of different protection alternatives. This paper presents a Dynamic Partial Reconfiguration-based fault injection methodology implemented by an integrated infrastructure for SEUs emulation in the configuration memory of Xilinx SRAM-based FPGAs. The proposed methodology exploits the Xilinx Essential Bits technology to extremely speed-up fault injection, ensuring correct operations of the fault injection infrastructure during the whole injection process.

Video-based navigation (VBN) is increasingly used in space applications to enable autonomous entry, descent, and landing of aircrafts. VBN algorithms require real-time performances and high computational capabilities, especially to perform features extraction and matching (FEM). In this context, field-programmable gate arrays (FPGAs) can be employed as efficient hardware accelerators. This paper proposes an improved FPGA-based FEM module. Online self-adaptation of the parameters of both the image noise filter and the features extraction algorithm is adopted to improve the algorithm robustness. Experimental results demonstrate the effectiveness of the proposed self-adaptive module. It introduces a marginal resource overhead and no timing performance degradation when compared with the reference state-of-the-art architecture.

If a camera moves while taking a picture, motion blur is induced. There exist mechanical techniques to prevent this effect to occur, but they are cumbersome and expensive. Considering for example an Unmanned Aerial Vehicle (UAV) engaged in a save and rescue mission, where recording frames of scene to identify people and animals to rescue is required. In such cases, weight of equipments is of absolute importance, and no extra hardware can be used. In such case, vibrations are unavoidably transmitted to the camera, and recorded frames are affected by blur. It is then necessary to deblur in real-time every frame to allow post-processing algorithms to extract the largest possible amount of information from them. For more than 40 years, numerous researchers have developed theories and algorithms for this purpose, which work quite well but very often require multiple different versions of the input image, huge amount of computational resources, large execution times or intensive parameters tuning.

In order to enable the non-cooperative rendezvous, capture, and removal of large space debris, automatic recognition of the target is needed. Video-based techniques are the most suitable in the strict context of space missions, where low-energy consumption is fundamental, and sensors should be passive in order to avoid any possible damage to external objects as well as to the chaser satellite.This paper presents a novel fast shape-from-shading (SfS) algorithm and a field-programmable gate array (FPGA)-based system hardware architecture for video-based shape reconstruction of space debris. The FPGA-based architecture, equipped with a pair of cameras, includes a fast image pre-processing module, a core implementing a feature-based stereo-vision approach, and a processor that executes the novel SfS algorithm.Experimental results show the limited amount of logic resources needed to implement the proposed architecture, and the timing improvements with respect to other state-of-the-art SfS methods. The remaining resources available in the FPGA device can be exploited to integrate other vision-based techniques to improve the comprehension of debris model, allowing a fast evaluation of associated kinematics in order to select the most appropriate approach for capture of the target space debris.

Nowadays Field-Programmable Gate Arrays (FP-GAs) are increasingly used in critical applications. In these scenarios fault tolerance techniques are needed to increase system dependability and lifetime. This paper proposes a novel methodology to achieve autonomous fault tolerance in FPGA-based systems affected by permanent faults. A design flow is defined to help designers to build a system with increased lifetime and availability. The methodology exploits Dynamic Partial Reconfiguration (DPR) to relocate at run-time faulty modules implemented onto the FPGA. A partitioning method is also presented to provide a solution which maximizes the number of permanent faults the system can tolerate. Experimental results highlight the negligible performance degradation introduced by applying the proposed methodology, and the improvements with respect to state-of-the-art solutions.

Video-based navigation is an increasingly used procedure with hard real-time requirements and high computational effort. In this field, FPGA hardware acceleration supplies low-cost and considerable performances enhancement. Video-based navigation algorithms extrapolate and correlate features from images, relying on their accuracy. Image enhancement provides more defined and contrasted frames, assuring high precision feature extraction. The paper introduces an FPGA-based self-adaptive image enhancer. The IP-core is suitable for hard-real time applications, such as space applications, thanks to the guaranteed high-throughput.

In order to enable the non-cooperative rendezvous, capture, and removal of large space debris, automatic recognition of the target is needed. Several technologies are currently available and stereo vision is one of the most suitable in the strict context of space missions, where low energy consumption is fundamental and sensors should be passive in order to avoid any possible damage to external objects as well as to the chaser satellite (e.g., scattered reflection of laser scanners may potentially be an issue). In this paper we are presenting a stereo vision system we set up in order to reconstruct the object model of space debris. Histogram equalization, executed by a programmable system-on-chip board equipped with a couple of cameras, and SIFT features extraction are the two fields of investigation. We identified the parameters that such a system have to deal with, and implemented a prototype solution tested in lab with debris mock up and actual satellite models. Results are demonstrating that fast image pre-processing is needed for having an acceptable recognition of object depth and shape. The proposed system can be integrated with other vision techniques to improve the comprehension of debris model allowing a fast evaluation of associated kinematics to select the most appropriate approach for capture.