An accurate junction temperature estimation is crucial for all reliability tests (e.g., power cycling tests) of power semiconductor devices, as it directly impacts the lifetime estimation. Studies on silicon carbide (SiC) MOSFETs demonstrates that conventional static temperature calibration methods can introduce significant error in virtual junction temperature determination due to the dynamic behaviour of the body diode’s voltage drop. In this study, a similar dynamic VSD behaviour was observed by switching the gate voltage without applying a load current, using only a sense current through the body diode, for two generations (Gen.3 and Gen.4) of double-trench SiC MOSFETs. However, this time-dependent dynamic VSD behaviour can be completely eliminated by applying sufficiently negative voltage for Gen.3 device. In contrast, dynamic VSD characteristic for Gen.4 is visible even at strongly negative gate voltage of -10 V. Furthermore, dynamic VSD behaviour is strongly influenced by gate loop inductance. Complementary 2D TCAD simulations replicating experimental conditions reveal that charge trapping and de-trapping at the gate and source-trench SiC/SiO2 interfaces, together with current sharing between the channel and body diode, fundamentally govern the observed transient VSD dynamics.

Reliability is a critical performance metric for power semiconductor switches and power electronic systems. Yet guidance on how to test and quantify that reliability is fragmented in the existing literature, particularly with the rapid adoption of wide-bandgap (WBG) devices and novel packaging technologies. This review brings guidance on what designers, reliability engineers, and researchers need to know about power cycling testing (PCT). We provide three major contents: first, introducing how new materials and packaging shift dominant failure mechanisms; second, comparing the main PCT standards joint electron device engineering council (JEDEC), automotive electronics council (AEC), international electrotechnical commission (IEC), and automotive qualification guideline (AQG) and explaining why the "test-to-fail" standard principle is overtaking legacy "test-to-pass" rules; and third, summarizing the unique challenges and existing solutions of applying PCT methods to WBG and ultra-WBG devices. Notably, to the best of the authors' knowledge, this is the first in-depth analysis of the newly released IEC 60749-34:2025 and AQG 324:2025, benchmarked against their earlier editions. Moreover, by collecting more than 200 testing samples from the existing literature, we also offer the first generic lifetime model that spans Si, SiC, multiple bond-wire materials, and die-attach technologies. Finally, the limitations and associated open questions are discussed to identify future research opportunities.

This paper will investigate influencing factors (gate voltage, switch on time etc.) on the dynamic behaviour of the source-drain voltage characteristic (V-SD) of SiC-MOSFETs. V-SD is a critical parameter needed for temperature read-out during the power cycling or other reliability test via the V-SD(T) method. 1200 V SiC MOSFETs from ten different manufacturers as well as chip generations with approximately same R-DSON of 80 m Omega were used in this work. If the off-gate voltage is not sufficiently negative during temperature read-out, a "run-in" behaviour of the forward voltage of the body diode up to a static value occurs for every manufacturer. This should be avoided when determining the temperature of the chip. Otherwise, large errors in temperature detection are likely and possible gate under- and overshoots due to high parasitic gate loops of a power cycling test benches have stronger impact on the transient response of the V-SD. Therefore, a sufficiently negative gate voltage should be applied to close the n-channel completely - in some cases even below the allowed datasheet value. Further, it has been confirmed that some manufacturers still face a transient V-SD response, although the gate voltage is already very negative, which could make the temperature read-out quite complicated. Furthermore, a small load current (similar to 1 A for example) has no influence depending on the test mode (MOSFET/3rd Quadrant) on the V-SD-response.

This paper investigates the lifetime of IGBTs in the TO-247 package using the power cycling test with and without switching losses to achieve the same temperature rise with different load currents. It has been found that the lifetime of the devices increases with shorter switch-on times (ton). An increase of 5 % in the forward voltage VCE,cold has been determined as the cause of failure. This is confirmed in the failure analysis with cracks between bond wire and metallization as well as with heel cracks determined by a pull test. An important factor when carrying out these tests is the method of chip-temperature ex-traction via a temperature sensitive electrical parameter (TSEP). Depending on the TSEP, different sensing regions of the chip are utilized, e.g. the pn-junction (backside location of the IGBT chip) or e.g. the RG,int (front-side location of the chip) [1, 2]. For instance, it was found that in tests with short ton the solder layer and the metallization (contact to bond wires) undergo different temperature swings. The difference in these temperature swings depend on the average temperature between these two layers and a difference of 10 K was determined at a temperature swing of 30 K and a ton of 30 ms. These temperature differences are significant and must therefore be taken into account during temperature extraction and when creating lifetime models and evaluating the test results, especially in the short ton region.

The aging of power modules in Heavy-Duty Fuel Cell Trucks is crucial because, as these modules age, their on-state resistance increases. This resistance growth leads to higher losses, especially in Si IGBTs and SiC MOSFETs, which in turn reduces the truck's operational efficiency. This study provides the findings from simulations of switching and conduction losses, which were conducted using a real mission profile and including the measured data from aged devices that display different levels of on-state resistance. This work presents an analysis of aged modules, where the focus is the comparison of both chip technologies. The total loss energy considering a real mission profile can be reduced with the designed SiC MOSFETs by 80 %.

The research paper focuses on physics-based reliability investigation of power module structures at substrate and component level which will be designed for various automotive applications. The direct copper bond (DCB) substrate is attached onto a copper heatsink by sintered silver of different thicknesses. Thermal and electrical conductivity of the sintered silver layers (360 ± 69 W/m•K and 39 ± 6 MS/m respectively) are determined and the microstructure is characterized by scanning electron microscopy (SEM) and electron backscatter diffraction (EBSD). Thermal cycle tests are conducted on the samples by experiment and numerical simulation. The degradation of sintered layer increases with number of thermal cycles. On component level, analysis has been performed on different power modules including die top system (DTS) and copper bond pad metallization (Cu AIT) on SiC chip. Active power cycle tests (APCT) and thermal shock tests (TST) are performed to analyze different reliability issues. Cu AIT has higher lifetime than die top system.

The evaluation of the bias temperature instability (BTI) or gate-switching instability (GSI) of the threshold voltage (Vth) is important for analyzing the stability of RDS,on and virtual temperature calculation by the VSD-T technique in the power cycling test (PCT). But before this, the Vth hysteresis should be first analyzed to choose the suitable Vth measurement parameters and eliminate the hysteresis effect on the BTI/GSI read-out. This paper investigates the Vth hysteresis of SiC MOSFETs under various measurement conditions. The differences in Vth hysteresis between different technologies are significant. Relevant measured and analytical results can provide the practical guidance for the BTI/GSI evaluation and the PCT for different types of SiC MOSFETs.

The improvement of the electrical properties of power semiconductors using engineered substrates is becoming increasingly significant. This paper investigates the dynamic performance and robustness of SiC MOSFETs based on SmartSiCTM engineered substrates, focusing on the reverse recovery of the body diode and their ruggedness under overload conditions such as short-circuit and surge current. A comparison with SiC MOSFETs based on conventional monocrystalline substrates was performed to evaluate the results. A significant decrease in reverse recovery charge was observed, particularly at higher temperatures, while the robustness during short-circuit type I and surge current was not affected.

The qualification of new generations of power electronic devices requires reliability testing, with Power Cycling (PC) being a standard method to evaluate the package related lifetime expectations under application-close conditions. In this paper, a double-trench SiC MOSFET, optimised for low forward conduction losses, is tested in PC forward mode and compared to body diode testing and hybrid mode testing. While forward mode testing followed the expected degradation patterns, body diode and hybrid mode testing in reverse direction showed unusual shifts, particularly affecting the temperature determination. The complications of testing in the reverse direction with an elevated current through the body diode are discussed in more detail.

In this work, discrete SiC MOSFETs with an RDS(ON) of 60 m Omega and a blocking capability of 1200 V have been subjected to extreme thermal shock tests and additional power cycling tests to study interactions between the failure modes in both tests. In this context, an Rth,jc (thermal resistance: junction - case) increase of up to 55 %, confirmed by found solder degradation in cross sections, can be noted after the thermal shock test. However, bond wire degradation remains the dominant cause of failure after the power cycling test, even if the solder layer of the test specimens was previously damaged.

In this paper, a new approach is presented to investigate the active short-circuit capability of SiC MOSFETs. This approach is utilized for 1200 V SiC MOSFET in a TO-247-4 package. It was found out that SiC MOSFETs can withstand higher current amplitudes during active short-circuit in the third quadrant compared to the first quadrant. The JFET-effect as well as the saturation current and its temperature dependence are decisive for this. The obtained findings are intended to contribute to the establishment of qualification standards for SiC MOSFETs with respect to their active short-circuit capability.

Nowadays, SiC components are increasingly used in the design of power modules. The packaging of such semiconductors is challenging due to the higher Young’s modulus of SiC devices. The resulting forces are affecting the reliability of such modules which is usually lower than modules with Si technology. In the past, the introduction of Danfoss BondBuffer technology (DBB) and sinter layers have significantly increased the reliability of Si-based modules. The combination of a SiC device with DBB within molding compound in a DCM module has shown a full potential in its lifetime increment. For this work, active power cycle test on unmolded and molded SiC power modules have been performed and analyzed via simulation. The results from both experiment and simulation showed that the lifetime of molded SiC module is significantly increased compared to reference unmolded test samples.

In this work, the power cycling capability of SiC MOSFETs in the TO-247 package from three different manufacturers (chip structure: planar, single trench and double trench) was investigated at different positive gate voltages during on-time (VGS,on = + 8 V … + 20 V). It was found that the TCP (temperature compensation point) of the RDS(ON) in a gate voltage range of 10 V to14 V is depending on the chip technology. The test results show that the power cycling capability decreases strongly when using gate voltages below the TCP. Therefore, the choice of the gate voltage should be considered for the test conditions. The cause of end-of-life failure is an increase in forward voltage by 5 %, resulting from distinct bond wire degradation.

Threshold voltage instability remains a challenging aspect for metal-oxide semiconductor-field-effect-transistors (MOSFETs) made from silicon carbide (SiC). SiC MOSFETs from two manufacturers, with planar and trench gate structure respectively, have been tested under different test procedures, including power cycling and high temperature gate bias tests. The standard power cycling test setup has been modified to enable an in situ threshold voltage read-out procedure with the hysteresis method. The recorded threshold voltage drift has been compared with results from high temperature gate bias tests applying a simple power law fit, with the intention to predict the drift in power cycling tests. For the group with trench MOSFETs comparable results between power cycling and gate stress tests have been achieved.

This research paper describes the reliability investigation of devices with SiC die on substrates and their lifetime estimation based on digital twin methodology. The most common failure modes that occur in power modules during power cycling and thermal cycling are bond wire degradation, die attach failures or system solder deterioration. The digital twin-based lifetime estimation helps to calculate the lifetime of power devices based on variable input parameters like temperature swing or minimum junction temperature of the chip etc. for example. This method develops a meta model of optimal prognosis file (MOP). It is shown that the inputs can be varied and the corresponding lifetime can be predicted.

In this paper, the threshold voltage shift during power cycling test for discrete SiC-MOSFET devices in TO-247 package from three different manufacturers with the same blocking capability of 1200 V is investigated. The temperature dependence of the threshold voltage plays a significant role in the interpretation of the results, since a change in V th can also influence common TSEP (temperature-sensitive electrical parameter) measurement methods. The tested devices have shown no deterioration of the solder layer, but degradation of the bond wires in the failure analysis.

In this work, discrete devices (Si IGBT and SiC MOSFET) have been tested at high power densities in power cycling tests. The power dissipation related to the total chip area was approx. 54.7 W/mm(exp 2) for the MOSFET and approx. 12.3 W/mm(exp 2) for the IGBT. These are the highest power densities that are currently realizable in an application-close test setup to our knowledge. All test specimens failed due to bond wire degradation and the failure mode was an increase in forward voltage. No change in the calibration curves, which were used for temperature determination during the power cycling test, is recognizable.

In this work, the influence of different thermal interface materials (TIMs) on junction temperature and power cycling capability of discrete Si IGBT in TO-247 package is investigated. A difference in the total thermal resistance (junction -heat sink) up to a factor of ten when using different heat conductive foils or paste is to be expected. A temperature deviation between the maximum junction temperature of up to 50 K is possible under the same conditions (i.e. equal, load current, Tvjmin, ton, VGE) during the power cycling test. If the current is increased to achieve the same Tvjmax, the power cycling capability is reduced. This influence and also the electrical insulating capacity of the different TIMs should be taken into account in the application. The cause of failure is bond wire degradation due to increase in forward voltage without solder deterioration in all power cycling tests.

This work investigates the power cycling capability of SiC MOSFETs $(60\ \mathrm{m}\Omega/1200\mathrm{V})$ in TO-247-packages with two different bonding configurations. As a result, a difference in lifetime by a factor of 1.5 to 2 is determined. The failure mode was an increase in forward voltage drop by degradation of the bond wire connection. The ANSYS simulations (thermal-electrical and mechanical) confirm that several thinner bond wires have a higher power cycling capability compared to a few bond wires with larger diameters.

The transient dual interface method (TDIM), proposed by the JEDEC 51-14 standard [1], determines the junction-to-case thermal resistance of power electronics with the separate point of two transient thermal impedance curves under different contact conditions. However, the influence of the junction temperature is not considered and this underestimates the actual value with earlier separation point. This phenomenon is presented first with experimental results at different junction temperatures. Electro-thermal finite element simulations and simulation with semiconductor physical behavior in the devices simulations are performed to explain the root reason. After that, the improved TDIM with the junction temperature compensation is proposed to improve the accuracy. The experimental results show that the improved TDIM improves the accuracy of about 9.5% for 600-V discrete IGBT devices.