This study investigates for the first-time repetitive avalanche pulses of SiC trench MOSFETs during first and third quadrant operation in a half-bridge configuration. Switching conditions and stray inductance were adapted to run both high side and low side MOSFETs into avalanche. Up to 30x106 cycles were applied and readouts were done in between. Reference tests with gate stress only and without avalanche mode were done for comparison. The devices did not show significant drifts in the main parameters nor any failures. Only C-V characteristics showed slight changes which can be explained as hole injection into the accumulation zone of the trench corner caused by avalanche. First and third quadrant operation did not show differences.

This study introduces a novel approach for in-situ device temperature probing in power transistors via dynamic measurement of the device current. By employing a transimpedance amplifier (TIA), the setup effectively captures fast self-heating effects with high accuracy. Experimental results reveal the significant impact of duty cycle, operating points, and ambient temperature on the thermal behavior of transistors. Simulations confirm the rapid temperature rise. This technique outperforms current methods by delivering very fast temperature data in the relevant current path inside the device. This advancement can enhance the accuracy of lifetime predictions and device modeling. Moreover, for the first time, the temperature inside the device can be resolved on a sub-& micro;s timescale, offering invaluable contributions to reliability engineering. Additionally, an extension of this method is used for extraction of self-heating-free ID-VDS characteristics. This cost-effective approach is compared with existing methods and its limitations are discussed critically.

An accurate junction temperature estimation is crucial for all reliability tests (e.g., power cycling tests) of power semiconductor devices, as it directly impacts the lifetime estimation. Studies on silicon carbide (SiC) MOSFETs demonstrates that conventional static temperature calibration methods can introduce significant error in virtual junction temperature determination due to the dynamic behaviour of the body diode’s voltage drop. In this study, a similar dynamic VSD behaviour was observed by switching the gate voltage without applying a load current, using only a sense current through the body diode, for two generations (Gen.3 and Gen.4) of double-trench SiC MOSFETs. However, this time-dependent dynamic VSD behaviour can be completely eliminated by applying sufficiently negative voltage for Gen.3 device. In contrast, dynamic VSD characteristic for Gen.4 is visible even at strongly negative gate voltage of -10 V. Furthermore, dynamic VSD behaviour is strongly influenced by gate loop inductance. Complementary 2D TCAD simulations replicating experimental conditions reveal that charge trapping and de-trapping at the gate and source-trench SiC/SiO2 interfaces, together with current sharing between the channel and body diode, fundamentally govern the observed transient VSD dynamics.

Accurate monitoring of junction temperature is essential for ensuring the reliable operation of silicon carbide (SiC) MOSFET-based power converters. This article presents a novel method for estimating junction temperature by utilizing the parasitic inductance voltage during the quasi-turn-on transient. The proposed approach inherently decouples the effects of load current and bypasses high-voltage isolation requirements, thereby eliminating the need for complex multi-parameter calibrations and reducing implementation complexity. The underlying physical mechanism and temperature dependence are examined through an equivalent circuit model, which yields an analytical expression. Double-pulse tests (DPT) verify its performance as a temperature sensitive electrical parameter under various operating conditions. A linearized mapping model that incorporates drain-source voltage facilitates real-time implementation. Experimental verification on a three-phase inverter platform demonstrates excellent agreement with fiber-optic temperature measurements, confirming the method's accuracy, practicality, and suitability for online junction temperature monitoring.

The insulated gate bipolar transistor module's degradation monitoring and identification play a crucial role in enhancing reliability. The bond-wire fatigue and solder layer degradation, as two prevalent degradation modes, are interactively coupled, which presents a significant challenge in accurately monitoring and characterizing the failure modes. To address this, a decoupled degradation monitoring method based on temperature-quantified indicators is proposed in this article. A rigorous electrothermal analysis derives the relationship between the temperature difference, power loss, and thermal parameters. The temperature differences at the half-cycle and full-cycle nodes of the power loss period are introduced to construct quantified indicators, which separately characterize two degradation modes. The proposed method only requires the two temperature difference nodes to monitor and quantify the aging states of the bonding wires and the solder layer. This method significantly reduces monitoring complexity and system costs, allowing for direct integration with pre-existing temperature monitoring methods. The simulation and experimental results have verified the validity of the proposed method.

Wide bandgap (WBG) semiconductor devices offer tremendous advantages over their silicon counterparts. Automotive applications benefit particularly from these advantages and, consequently, the automotive sector has emerged as the lead application for silicon carbide (SiC) devices and will also play an important role for gallium nitride (GaN) power devices. SiC components in particular have been used in commercial automotive products for several years and meet the usual qualification standards in terms of robustness and reliability. However, the silicon-based standards do not cover all peculiarities that the WBG devices exhibit. Bipolar degradation and gate switching instability (GSI) are only two of the effects that do not affect silicon. Also, the degradation of the devices throughout their service life can be different from that of silicon devices. Therefore, the existing standards have to be amended to offer the same security level for WBG devices, which is essential for the success in the extremely robust and reliability-sensitive automotive sector. Furthermore, the production maturity is not yet on the same level as the silicon technology. Besides conservative device design, particular screening tests are required. If such procedures are not viable, even complex and demanding burn-in tests might be implemented to cover all relevant defects and degradation mechanisms and ensure the quality that the automotive industry demands to maintain their reliability level. This work provides a review of the current status of WBG device reliability with respect to automotive requirements and of the ongoing activities to catch up with the level of silicon devices.

This work investigates the short-circuit (SC) robustness of 1200 V SiC MOSFETs from two different manufacturers (M1: trench-gate, M2: planar-gate) up to their destruction limits. Both devices, packaged in TO-247 4-pin housings with a nominal on-state resistance ( R ds ,on ) of 80 mΩ, were systematically tested under a gate-source voltage of V GS,on =15 V and at a fixed DC-link voltage of 800 V. In addition to determining the SC withstand capability, the study focuses on the influence of the negative gate bias ( V GS,off ​) on device robustness. Results show that SC capability and dominant failure mechanisms are strongly dependent on gate technology as well as on the applied V GS,off ​. Trench-gate M1 devices primarily fail due to gate oxide degradation under strong negative bias, while planar-gate M2 devices exhibit failures linked to parasitic BJT activation at SC turn-off or thermal runaway at V GS,off ​= 0 V. Additionally, TCAD simulations closely reproduce the measured trends and provide physical insight into the failure mechanisms. The experimental–simulation approach establishes a comprehensive understanding of SC robustness limits and failure types in state-of-the-art SiC MOSFET technologies.

Reliability is a critical performance metric for power semiconductor switches and power electronic systems. Yet guidance on how to test and quantify that reliability is fragmented in the existing literature, particularly with the rapid adoption of wide-bandgap (WBG) devices and novel packaging technologies. This review brings guidance on what designers, reliability engineers, and researchers need to know about power cycling testing (PCT). We provide three major contents: first, introducing how new materials and packaging shift dominant failure mechanisms; second, comparing the main PCT standards joint electron device engineering council (JEDEC), automotive electronics council (AEC), international electrotechnical commission (IEC), and automotive qualification guideline (AQG) and explaining why the "test-to-fail" standard principle is overtaking legacy "test-to-pass" rules; and third, summarizing the unique challenges and existing solutions of applying PCT methods to WBG and ultra-WBG devices. Notably, to the best of the authors' knowledge, this is the first in-depth analysis of the newly released IEC 60749-34:2025 and AQG 324:2025, benchmarked against their earlier editions. Moreover, by collecting more than 200 testing samples from the existing literature, we also offer the first generic lifetime model that spans Si, SiC, multiple bond-wire materials, and die-attach technologies. Finally, the limitations and associated open questions are discussed to identify future research opportunities.

This paper will investigate influencing factors (gate voltage, switch on time etc.) on the dynamic behaviour of the source-drain voltage characteristic (V-SD) of SiC-MOSFETs. V-SD is a critical parameter needed for temperature read-out during the power cycling or other reliability test via the V-SD(T) method. 1200 V SiC MOSFETs from ten different manufacturers as well as chip generations with approximately same R-DSON of 80 m Omega were used in this work. If the off-gate voltage is not sufficiently negative during temperature read-out, a "run-in" behaviour of the forward voltage of the body diode up to a static value occurs for every manufacturer. This should be avoided when determining the temperature of the chip. Otherwise, large errors in temperature detection are likely and possible gate under- and overshoots due to high parasitic gate loops of a power cycling test benches have stronger impact on the transient response of the V-SD. Therefore, a sufficiently negative gate voltage should be applied to close the n-channel completely - in some cases even below the allowed datasheet value. Further, it has been confirmed that some manufacturers still face a transient V-SD response, although the gate voltage is already very negative, which could make the temperature read-out quite complicated. Furthermore, a small load current (similar to 1 A for example) has no influence depending on the test mode (MOSFET/3rd Quadrant) on the V-SD-response.

This paper investigates the short-circuit behavior of SiC MOSFETs in a quasi series connection, a scenario that can be found in more complex topologies, but also in simple two-level phase legs. Besides a theoretical analysis, short-circuit tests for such scenarios are carried out with state-of-the-art 3.3-kV SiC MOSFET half-bridge modules. The analysis particularly focuses on the voltage distribution between the switches within a half-bridge module, evaluating the impact of different device parasitics with impact on the gate circuit.

Gate switching instability (GSI) has recently been found to be a prominent degradation mechanism in Silicon Carbide (SiC) MOSFETs under certain stress conditions. In this paper we present a broad investigation of gate switching stress (GSS) parameters affecting GSI. Various 1.2 kV planar and trench SiC MOSFETs were utilized to cover a wide range of distinct device technologies. It was found that high operating temperatures and high (transient and static) gate off-state voltages lead to a stronger degradation of the gate threshold voltage. However, threshold voltage drift estimations up to an applicationnear number of switching cycles are located within device limits. Additional CV and sub-threshold measurements revealed stress-related modifications of the charge state at the $\text{SiC} / \text{SiO}_{2}$ interface. Furthermore, drifts of the on-resistance correlated with the GSS driven increase of the threshold voltage.

This work investigates the impact of gate driving conditions on the short-circuit withstanding time (SCWT) of Schottky and ohmic gate p-GaN HEMTs under single-event conditions. A modular test setup with low stray inductance (Lstray < 15 nH) is developed to evaluate both switching behavior and short-circuit (SC) robustness under uniform test configuration. For the Schottky gate (SG) device, the experimental results indicate that increasing gate resistance (RG) enhances the SCWT at critical DC-link voltage (VDC above 350 V) by reducing the peak SC power. In the ohmic gate device, the device switching voltage slope can be well controlled by varying the boost resistance over a wide range. For SC capability investigation, the SCWT at critical VDC exhibits sensitivity to the gate boost current (IG,ON). A trade-off between IG,ON, and SCWT is deduced based on the experimental results. Furthermore, three temperature estimation methods are compared for SG device: the Cauer thermal model method, an energy-based calculation method, and using gate leakage current (IGSS) as a temperature-sensitive electrical parameter (TSEP). Each method presents its limitations, but all indicate a high junction temperature (Tj) over 300 degrees C during the SC event at nearly failure voltage, signaling critical local temperature behavior.

The single-phase cascaded H-bridge multilevel converter (CHBMC) stands out as a prominent topology in medium- and high-voltage applications due to its scalability and modularity. However, the CHBMC may encounter multiple open-circuit (OC) switch faults, leading to significant degradation in both dc voltages and grid current. To facilitate fault-tolerant operation postidentification of multiple OC switches, conventional approaches typically involve adjusting phase angles in the pulsewidth modulation. This, however, results in complex control loops for dc voltage balancing and lacks flexibility. This article proposes a simple fault-tolerant control (FTC) technique based on online vector calculation and a constraint mechanism to simultaneously address multiple objectives, including dc voltage balancing, reduction of grid current total harmonic distortion, and even power distribution following OC switch faults in the CHBMC. Depending on the specific OC switches involved, the voltage levels of healthy or faulty power cells are automatically calculated and adjusted using vector constraints to maintain balanced dc voltages and mitigate current harmonics. Subsequently, the resulting vectors are flexibly determined to meet the requirements of reduced voltage stress and even power distribution. This technique is independent of voltage levels and easily extended to the single-phase CHBMC with more faulty power cells. Experimental results validate the effectiveness of the proposed FTC technique.

In this work, parameters influencing the dynamic on-state resistance R-DS,R-on are investigated and discussed for different technologies of normally-off GaN HEMT devices. Therefore, the focus is on the trajectory during switching, the off-state preconditioning time, the timing of the R-DS,(on) readout as well as gate drive condition. All investigated GaN devices are affected by trapping at long-term preconditioning via V-DS. The recovery times range from ms up to hours. Hence, conditions with <= 1 s have been pursued in a soft switching methodology. The variation of the gate voltage is present as an offset and the dynamic RDS, on can decay faster at high drain bias. For currentdriven GITs, the gate current IG can further accelerate the recovery, and a good boost-link design mitigates dynamic effects. An additional hard switching stress is included by adding a capacitive load. Changes are mainly present in the first 2 mu s and thus a fast timing of the readout is very important. In hard switching stress the dynamic R-DS,R-on is larger at higher drain bias.

In a bid to adapt power cycling tests as closely as possible to the actual application conditions, tests with both conduction and switching losses are becoming more common. In this article, the influence of switching losses on power cycling lifetime is studied for discrete SiC mosfets. Four switch-mode power cycling tests with different switching loss magnitudes are performed in both clamped and unclamped inductive switching modes. Classical dc power cycling tests in mosfet and body-diode modes are also conducted as reference tests. It is found that switching losses up to 17 mJ have no observable influence on power cycling lifetime, where only package failures are considered. This means that a junction temperature swing of up to 45 K, lasting a few microseconds, does not accelerate bond wire or solder layer degradations. However, when the switch-mode test is used, the drop in junction temperature during the measurement of VDS-hot (for solder layer degradation monitoring) must be taken into account. Drifts in the gate threshold voltage as well as gate and drain leakage currents were found to depend on the test approach.

This paper investigates the lifetime of IGBTs in the TO-247 package using the power cycling test with and without switching losses to achieve the same temperature rise with different load currents. It has been found that the lifetime of the devices increases with shorter switch-on times (ton). An increase of 5 % in the forward voltage VCE,cold has been determined as the cause of failure. This is confirmed in the failure analysis with cracks between bond wire and metallization as well as with heel cracks determined by a pull test. An important factor when carrying out these tests is the method of chip-temperature ex-traction via a temperature sensitive electrical parameter (TSEP). Depending on the TSEP, different sensing regions of the chip are utilized, e.g. the pn-junction (backside location of the IGBT chip) or e.g. the RG,int (front-side location of the chip) [1, 2]. For instance, it was found that in tests with short ton the solder layer and the metallization (contact to bond wires) undergo different temperature swings. The difference in these temperature swings depend on the average temperature between these two layers and a difference of 10 K was determined at a temperature swing of 30 K and a ton of 30 ms. These temperature differences are significant and must therefore be taken into account during temperature extraction and when creating lifetime models and evaluating the test results, especially in the short ton region.

In this paper, the influence of device parameters spread on current sharing during power cycling test is investigated. The contribution of the asymmetry of thermal paths below individual chips to the distribution of temperature among paralleled chips in a module is also investigated. When paralleled, the IGBT chips share conduction losses based on their saturation collector-emitter voltages (VCEsat). They also share switching losses based on their gate threshold voltage (VGEth) and trans-conductance (gm). A baseplate-less IGBT module with two paralleled chips per switch was subjected to power cycling test using two approaches: by heating it with only conduction losses (classical DC test) and by heating it using both conduction and switching losses (switching-mode test). It was found that the most important parameter influencing lifetime in this module was the asymmetry in thermal paths under individual chips. Both DC-mode and switching-mode tests resulted in similar lifetime. In both cases, devices failed by either solder delamination or bond wire lift-off.

In this paper, the switching behavior of SiCMOSFET modules with integrated monolithic silicon RCsnubbers (SiRC-snubber) are investigated. SiC-MOSFETs have many advantages over more common technologies e.g. SiIGBTs. One of these advantages is the high switching speed. This potential often cannot be fully utilized due to parasitic inductances with combined high overvoltages and/or EMC issues. Therefore, the switching speed has to be limited to stay inside the specs of the individual device. This limitation can be reduced using a SiRC-snubber that can be integrated inside the power module. To investigate the influence during switching, a 750 V SiC-MOSFET module with integrated SiRC-snubber soldered on the DCB is tested. The switching behavior of the SiC-MOSFET body diode with and one without SiRC-snubber is compared. The results show that oscillations and voltage overshoots during switching can be drastically reduced. Further, the power-device losses can also be reduced.

A new test method is introduced that targets bipolar degradation of SiC MOSFET devices during short dead time phases. The approach offers strong scalability and acceleration, considers application-compliant conditions, and can cover current levels several times beyond the nominal current. Initial tests at short dead times are presented, analyzed, and compared with corresponding worst-case reference tests under DC conditions.

The aging of power modules in Heavy-Duty Fuel Cell Trucks is crucial because, as these modules age, their on-state resistance increases. This resistance growth leads to higher losses, especially in Si IGBTs and SiC MOSFETs, which in turn reduces the truck's operational efficiency. This study provides the findings from simulations of switching and conduction losses, which were conducted using a real mission profile and including the measured data from aged devices that display different levels of on-state resistance. This work presents an analysis of aged modules, where the focus is the comparison of both chip technologies. The total loss energy considering a real mission profile can be reduced with the designed SiC MOSFETs by 80 %.