Acquiring images of the layout of integrated circuits increases the demands on electron microscopy as the technology scaling continues. Each new chip generation makes producing stable and processable image quality more difficult. Currently, no automated, technology-agnostic solution supports the human operator in creating optimal layout images. Therefore, we propose an image quality assessment framework that determines the optimal microscope settings for each technology sample. We define the optimal settings as the minimum possible scan time, which still maintains the processability of the acquired images. The two implemented machine learning algorithms do not require a noise and distortion-free reference image. We compare both models on an updated version of the REFICS dataset and investigate their behavior for different noise types. Finally, we use our framework to fully recover the layout of a 28nm technology, reducing scan time by more than 95%.

Considering the potential risks of piracy and malicious manipulation of complex integrated circuits using worldwide distributed manufacturing sites, an effective and efficient reverse engineering process allows the verification of the physical layout against the reference design. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the recovery of the design from a physical device. Using this reverse engineering process on a physical chip layout, a circuit graph based partitioning of circuit blocks and an Elliptic Curve Cryptography (ECC) module identification will be performed. For the first time, the error between the generated layout and the design GDS layout will be compared quantitatively as a figure of merit (FoM). We propose a new classification of malicious manipulations based on their layout impact.

In view of potential risks of piracy and malicious manipulation of complex integrated circuits built in technologies of 45 nm and less, there is an increasing need for an effective and efficient process of reverse engineering. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the extraction of a layout. For the first time the error between the generated layout and the known drawn GDS will be compared quantitatively as a figure of merit (FOM). From this layout a circuit graph of an ECC encryption and the partitioning in circuit blocks will be extracted.