Deep reinforcement learning is shown to improve the design cost of hardware char63software interfaces within an industrial design framework. Based on optimization preferences specified by a designer, the proposed approach generates optimized solutions.

As various domain knowledge is prerequired, the embedded systems development is difficult. In the development process, multiple programming languages are used to develop different aspects such as hardware, firmware and formal verification. The semantic gap and inconsistent syntax among these languages escalate further the design efforts. We propose to generate Python-embedded Self-Verifying Domain-Specific Languages (DSLs) from metamodels. Domainspecific semantics are captured in metamodels. With additional configurations, domain-specific functionalities are included in DSLs. Further, tests are generated to assure the DSL quality. To demonstrate the applicability, the proposed approach is applied on an embedded system automation framework that generates hardware, firmware and formal properties for verification. An SoC was generated and verified with the automation framework. Minimal efforts were observed to achieve high code coverage for DSLs. Furthermore, our approach scales well with increasing domain complexity, i.e., the generation took less than 10 seconds for the most complex DSL (129.9k Lines of Code).

Fault simulation is a technique used to evaluate the robustness of safety-critical systems. An objective of the technique is to inject faults into a system and to observe its behavior. To deal with the large and complex designs, fast and valid fault simulation techniques are highly demanded. For this purpose fault simulators are used. Fault simulators are software programs that facilitate fault injection on a design model and capture the responses of a design for different fault types. This paper explores methods for extending a hardware simulator with fault injection capability. We consider Verilator, an open source hardware simulator, for fault simulation of complex designs. Towards this end, we extend Verilator with fault injection capability. Verilator’s high performance combined with the added functionality for fault modeling provides accurate and fast results to measure the dependability and robustness of designs. To evaluate and validate the approach, different fault models were injected into several designs. The experimental results show an average slowdown of 23% of the simulator runtime. Furthermore, the technique was used to evaluate the dependability of an SoC with a safety related software flow monitoring algorithm.

Concrete repair of the Starzenbach duct in Feldafingen with carbon concrete Repairing concrete structures with carbon reinforced textile concrete under wet conditions or even underwater is not yet taken in to account according to the German abZ. Nonetheless, it can be assumed that there is a high potential for application in outdoor areas /facilities like channels or sewers which are fully exposed to weathering or even partially flooded with water. Recent research already shows that there are possibilities of applying textile reinforced carbon concrete under such conditions, which finally led to the entitled pilot project that has already successfully been completed. This project was a highly damaged duct liable to collapse in the centre of Feldafingen. The repair must be performed as quickly as possible while traffic and thus access to the adjacent properties must be granted. To meet these requirements, it was necessary to combine the standardised shotcrete method with still developing carbon concrete technology and perform extensive underwater tests prior to the project itself. It was possible to restore the duct with an additional layer of only 70 mm thickness. Furthermore, the flow speed of the water was improved by the seamless and smooth surface of the carbon concrete.

Development of a partial safety factor for high strength grouts in offshore applications During the design of grouted connections in offshore applications (wind turbines and platforms), the fundamental material interrelationships are derived primarily on the basis of DIN EN 1992 which is applicable to the design and construction of building of concrete, reinforced concrete and pre-stressed concrete. In the paper at hand the application of the design value for the compressive strength of concrete f(cd) to modern, high performance grouts is discussed. Firstly, the components of the design value for the compressive strength of concrete f(cd) are presented in detail and it is then discussed how in the safety concept within the standards variances are considered in the underlying assumptions and uncertainties are taken into account during their determination. Coefficients of variation were determined based on values of compressive strength from realistic and offshore-typical grouting experiments, which were applied during the determination of the partial safety factor for grout gamma(G). The applicability of the design value of the compressive strength of concrete f(cd) under consideration of the derived partial safety factor for grout gamma(G) was subsequently tested and compared to the design value of DIN EN 1992.

The complexity of today's System on Chips (SoCs) forces designers to use higher levels of abstractions. Here, early design decisions are conducted on abstract models while different configurations describe how to actually realize the desired SoC. Since those decisions severely affect the final costs of the resulting SoC (in terms of utilized area, power consumption, etc.), a fast and accurate cost estimation is essential at this design stage. Additionally, the resulting costs heavily depend on the adopted logic synthesis algorithms, which optimize the design towards one or more cost objectives. But how to structure a cost estimation method that supports multiple configurations of an SoC, implemented by use of different synthesis strategies, remains an open question. In this work, we address this problem by providing a cost estimation method for a configurable SoC using Machine Learning (ML). A key element of the proposed method is a data representation which describes SoC configurations in a way that is suited for advanced ML algorithms. Experimental evaluations conducted within an industrial environment confirm the accuracy as well as the efficiency of the proposed method.

Development of a partial safety factor for high strength grouts in offshore applications During the design of grouted connections in offshore applications (wind turbines and platforms), the fundamental material interrelationships are derived primarily on the basis of DIN EN 1992 which is applicable to the design and construction of building of concrete, reinforced concrete and pre-stressed concrete. In the paper at hand the application of the design value for the compressive strength of concrete f cd to modern, high performance grouts is discussed. Firstly, the components of the design value for the compressive strength of concrete f cd are presented in detail and it is then discussed how in the safety concept within the standards variances are considered in the underlying assumptions and uncertainties are taken into account during their determination. Coefficients of variation were determined based on values of compressive strength from realistic and offshore-typical grouting experiments, which were applied during the determination of the partial safety factor for grout γ G . The applicability of the design value of the compressive strength of concrete f cd under consideration of the derived partial safety factor for grout γ G was subsequently tested and compared to the design value of DIN EN 1992.

Generating instead of implementing variable design platforms is becoming increasingly popular in the development of System on Chips (SoCs). This shift also poses the challenge of rapid compiler optimization that adapts to each newly generated platform. In this paper, we evaluate the impact of 104 compiler flags on memory usage and core execution time against standard optimization levels. Each flag has a different influence on these costs, which is difficult to predict. In this work, we apply cost estimation methods to predict the impact of each flag on the generated core using unsupervised Machine Learning (ML), in the form of k-means clustering. The key strengths of the approach are the low need for data, the adaptability to new cores, and the ease of use. This helps the designer to understand the impact of flags on related applications, showing which combination is optimizing the most. As a result, we can obtain 20,93% optimization on the software size, 3,10% on the performance, and 1,75% on their trade-off beyond the -03 optimization.

The HW/SW interface is a common and crucial component in System-on-Chips, enabling the interaction between software and hardware. Generating architecture and firmware code of the interface from extended IP-XACT, SystemRDL, or proprietary formalism is an established technology. This paper describes a new area and performance optimization step in the HW/SW interface generation process that reduces the silicon area and hardware access time through firmware. Three improvements of the underlying formalism are applied to achieve the optimization: First, a decoupling of bit fields from registers, which allows the rearrangement of the memory layout easily. Second, the specification of hardware accesses, which constraints the bit field arrangement. Third, different implementations of bit field accesses, such as memory-mapped or via CPU special registers. The used generation framework follows the approach of model-driven architecture, which includes optimization. Initially, abstract models specify the requirements of the IP or the HW/SW interface. Transformations turn these models into platformindependent models of hardware and firmware. These models are further transformed into implementation-specific models of a target language, such as hardware description languages or C. The proposed optimization has been successfully applied to peripheral variants of a CPU subsystem used in an industrial demonstrator. An area reduction of 19% and a performance gain of 11% has been achieved by optimizing the interfaces.

With the increase in the complexity of the modern System on Chips (SoCs) and the demand for a lower time-to-market, automation becomes essential in hardware design. This is particularly relevant in complex/time-consuming tasks, as the optimization of design cost for a hardware component. Design cost, in fact, may depend on several objectives, as for the hardware-software trade-off. Given the complexity of this task, the designer often has no means to perform a fast and effective optimization-in particular for larger and complex designs. In this paper, we introduce Deep Reinforcement Learning (DRL) for design cost optimization at the early stages of the design process. We first show that DRL is a perfectly suitable solution for the problem at hand. Afterwards, by means of a Pointer Network, a neural network specifically applied for combinatorial problems, we benchmark three DRL algorithms towards the selected problem. Results obtained in different settings show the improvements achieved by DRL algorithms compared to conventional optimization methods. Additionally, by using reward redistribution proposed in the recently introduced RUDDER method, we obtain significant improvements in complex designs.

Repairing concrete structures with carbon reinforced textile concrete under wet conditions or even underwater is not yet taken in to account according to the German abZ. Nonetheless, it can be assumed that there is a high potential for application in outdoor areas /facilities like channels or sewers which are fully exposed to weathering or even partially flooded with water. Recent research already shows that there are possibilities of applying textile reinforced carbon concrete under such conditions, which finally led to the entitled pilot project that has already successfully been completed. This project was a highly damaged duct liable to collapse in the centre of Feldafingen. The repair must be performed as quickly as possible while traffic and thus access to the adjacent properties must be granted. To meet these requirements, it was necessary to combine the standardised shotcrete method with still developing carbon concrete technology and perform extensive underwater tests prior to the project itself. It was possible to restore the duct with an additional layer of only 70 mm thickness. Furthermore, the flow speed of the water was improved by the seamless and smooth surface of the carbon concrete.

Depuis le début du xixe siècle, l'activité musicale a été considérée par beaucoup comme un moyen d'élévation morale des classes populaires. Censée permettre la pacification des relations sociales et le dépassement du traumatisme de la Révolution, la musique est également entrée dans les projets de formation du mouvement ouvrier naissant. La tension entre une fonction de démocratisation de la culture et une tendance à conforter les distinctions sociales a, pendant deux siècles, dominé les pratiques musicales des sociétés européennes.

Hardware/software co-designs are usually defined at high levels of abstractions at the beginning of the design process in order to provide a variety of options on how to realize a system. This allows for design exploration which relies on knowing the costs of different design configurations (with respect to hardware usage and firmware metrics). To this end, methods for cost estimation are frequently applied in industrial practice. However, currently used methods oversimplify the problem and ignore important features, leading to estimates which are far off from real values. In this article, we address this problem for memory systems. To this end, we borrow and re-adapt solutions based on Machine Learning (ML) which have been found suitable for problems from the domain of Computer Vision (CV). Based on that, an approach is proposed which outperforms existing methods for cost estimation. Experimental evaluations within an industrial context show that, while the accuracy of the state-of-the-art approach is frequently off by more than 20 percent for area estimation and more than 15 percent for firmware estimation, the method proposed in this article comes rather close to the actual values (just 5-7 percent off for both area and firmware). Furthermore, our approach outperforms existing methods for scalability, generalization, and decrease in manual effort.

Considering the potential risks of piracy and malicious manipulation of complex integrated circuits using worldwide distributed manufacturing sites, an effective and efficient reverse engineering process allows the verification of the physical layout against the reference design. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the recovery of the design from a physical device. Using this reverse engineering process on a physical chip layout, a circuit graph based partitioning of circuit blocks and an Elliptic Curve Cryptography (ECC) module identification will be performed. For the first time, the error between the generated layout and the design GDS layout will be compared quantitatively as a figure of merit (FoM). We propose a new classification of malicious manipulations based on their layout impact.

In view of potential risks of piracy and malicious manipulation of complex integrated circuits built in technologies of 45 nm and less, there is an increasing need for an effective and efficient process of reverse engineering. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the extraction of a layout. For the first time the error between the generated layout and the known drawn GDS will be compared quantitatively as a figure of merit (FOM). From this layout a circuit graph of an ECC encryption and the partitioning in circuit blocks will be extracted.

Background: We present the long-term results of remodeling of the glenohumeral joint alter open subscapularis elongation and relocation of the humeral head in patients with an internal rotation contracture and joint incongruity due to brachial plexus birth palsy. Methods: In this before-and-after study, 61 patients who underwent open subscapularis elongation and reduction of the glenohumeral joint were evaluated with respect to joint remodeling, with a mean follow-up period of 10.2 years (range, 7-16 years). The mean age at operation was 3.2 years (range, 8 months to 15 years). Measurements of the percentage of the humeral head anterior to the midscapular line (PHHA), glenoid version, and diameter of the humeral head were recorded using magnetic resonance imaging, comparing the affected joints preoperatively vs. postoperatively (n = 31) and comparing the operated vs. unaffected sides postoperatively (n = 61). Results: The mean increase in PHHA was 27.6 percentage points (95% confidence interval, 22.4-32.7 percentage points; P < .01), from 13.2% to 40.8%. The glenoid retroversion changed by 14.8 degrees (95% confidence interval, 11.1 degrees-18.4 degrees; P < .01), from 25.4 degrees to 10.6 degrees, approaching a normal value. All patients, even those older than 5 years, showed a clear benefit from surgery. Conclusions: Our study confirms that open subscapularis lengthening with joint repositioning, up to the age of 5 years, gives consistent remodeling of incongruent shoulders with surprisingly small differences between the operated and unaffected shoulders at long-term follow-up. The findings indicate that open reduction is useful also in adolescents and challenges the notion that older children should be treated with derotational humeral osteotomy. (C) 2019 Journal of Shoulder and Elbow Surgery Board of Trustees. All rights reserved.

Developing software in a slightly different way can have a dramatic impact on soft error resilience. This observation can be transferred in a process of improving existing code by transformations. These transformations are of systematic nature and can be automated. In this paper, we present a framework for low level embedded software generation - commonly referred to as firmware - and the inclusion of safety measures in the generated code. The generation approach follows a three stage process starting with formalized firmware specification using both platform dependent and independent firmware models. Finally, C-code is generated from the view model in a straight forward way. Safety measures are included either as part of the translation step between the models or as transformations of single models.

Developing software in a slightly different way can have a dramatic impact on soft error resilience. This observation can be transferred in a process of improving existing code by transformations. These transformations are of systematic nature and can be automated. In this paper, we present a framework for low level embedded software generation - commonly referred to as firmware -- and the inclusion of safety measures in the generated code. The generation approach follows a three stage process starting with formalized firmware specification using both platform dependent and independent firmware models. Finally, C-code is generated from the view model in a straight forward way. Safety measures are included either as part of the translation step between the models or as transformations of single models.

With the advancement of Internet of Things, the cost of System-on-Chips (in terms of area, performance, etc.) becomes increasingly relevant for realizing affordable as well as performant devices. Although System-on-Chips are very diverse with respect to specifications and requirements, some components are ubiquitous. One of them is the Hardware/Software Interface, which serves for controlling communication and interconnected functionalities between Hardware and Software. Motivated by their common use, the implementation of optimized interfaces towards certain costs (in terms of area, performance, etc.) becomes a central problem in the design of embedded systems. In this work we introduce a novel optimization method for minimizing the cost of Hardware/Software Interfaces using Convolutional Neural Networks coupled with Evolutionary Algorithms.

This paper presents an automated process for end-to-end embedded system design following OMG's model driven architecture (MDA) vision. It tackles a major challenge in automation: bridging the large semantic gap between the specification and the target code. The shown MDA adaption proposes an uniform and systematic way by splitting the translation process into multiple layers and introducing design platform independent and implementation independent views.In our adaption of MDA, we start with a formalized specification and we end with code (view) generation. The code is then compiled (software) or synthesized (hardware) and finally assembled to the embedded system design. We split the translation process in Model-of-Thing (MoT), Model-of-Design (MoD) and Model-of-View (MoV) layers. MoTs represent the formalized specification, MoDs contain the implementation architecture in a view independent way, and MoVs are implementation dependent and view dependent, i.e., specific details in target language.MoT is translated to MoD, MoD is translated to MoV and MoV is finally used to generate views. The translation between the Models is based on templates, that reflect design and coding blueprints. The final step of the view generation is itself part of generation. The Model MoV and the unparse method are generated from a view language description.The approach has been successfully adapted for generating digital hardware (RTL), properties for verification (SVA), and snippets of firmware that have been successfully synthesized to an FPGA.