Three-dimensional multi-channel field-effect transistor (MCFET) gate stack and series resistance are investigated and optimized by specifically developed integration processes, characterization methods, and numerical simulations. First, the impact of a TiN/HfO 2 gate stack on embedded-gate MCFET structure performance is studied. Both TiN/SiO 2 and N + poly-Si/SiO 2 gate stacks were introduced in the MCFET to compare the carrier mobility behavior (300 K down to 20 K), the gate leakage current, and the negative bias temperature instability. The obtained electrical data are then compared with a planar FD-SOI reference, highlighting some specific challenges linked to the introduction of a high- kappa/metal gate stack in embedded cavities. On the other hand, it is shown how the series resistance is intrinsically increased by the 3-D configuration. We also show how this increase can be attenuated significantly by optimizing the source/drain (S/D) shape, the implantation conditions, and the S/D silicide position.

Multi-Channel Field-Effect Transistor (MCFET) structures with ultralow IOFF (16 pA/mum) and high ION (N: 2.27 mA/mum and P: 1.32 mA/mum) currents are obtained on silicon on insulator (SOI) with a high-kappa/metal gate stack, satisfying both low-standby-power and high-performance requirements. The experimental current gain of the MCFET structure is compared with that of an optimized planar FD-SOI reference with the same high-kappa/metal gate stack and is quantitatively explained by an analytical model. Transport properties are investigated, and the specific MCFET electrostatic properties are evidenced, in particular a higher VDsat for MCFETs compared with the planar reference. Finally, through 3-D numerical simulations correlated with specific characterizations, the influence of the channel width on the electrical performance is analyzed. For narrow devices, the parasitic bottom channel increases the total drain current of the MCFET structure without degrading the electrostatic integrity.

For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic CV/I delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent I ON /I OFF characteristics (NMOS: 2.33 mA/mum at 27 pA/mum and PMOS: 1.52 mA/mum at 38 pA/mum). A gate capacitance C gg reduction of 32% is measured, thanks to S -parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain A VI ( = gm / g ds ) is improved by 92%.