In many embedded systems, the computational power of an instruction set processor is combined with hardware accelerators. Building such combined systems implies co-design of the software that runs on the processor and the hardware that accelerates the embedded application. During the co-design process, the application is partitioned into a software part (running on the processor) and a hardware part (running on the accelerator). In order to ease the iterative process of partitioning, we introduce a novel design methodology. In our methodology, the interface between hardware and software is transparent to the software designer, and is based on dynamic method interception. Because the interface is transparent and generated automatically, the initial all-software prototype of the system can more easily be refined and partitioned. We show that method interception is inexpensive, and we demonstrate method interception in a real-life application.Using our methodology, embedded systems can be designed fast, reducing time-to-market, while still achieving a high run-time performance.

In distributed hybrid computing systems, traditional sequential processors are loosely coupled with reconfigurable hardware for optimal performance. This loose coupling proves to be a communication challenge; the processor units cannot efficiently share a physical memory. This paper proposes a distributed shared memory architecture and a method for effective data migration within that shared memory. Data is moved using a novel garbage collection scheme, the dual semispace collector. The new garbage collector and the distributed memory prove to be an effective means of data migration in distributed hybrid computing systems.

Client-side diversification led the video-coding community to develop scalable video-codecs supporting efficient decoding at varying quality levels. This scalability has a lot of advantages but the corresponding decoding algorithm is complex and really stresses the system bandwidth as it replaces the blockbased DCT-approach with frame-based wavelets. This has a tremendous impact on the hardware architecture.We present the implementation of the RESUME decoder using reconfigurable hardware designed through the use of state-of-the-art HW/SW-codesign techniques. These techniques were augmented with automatic loop transformations and regression testing. Our efforts resulted in a design capable of decoding more than 25 frames per second at lossless CIF resolution.

In the RESUME project we developed a real-time FPGA prototype of a fully scalable, wavelet based video decoder which overcomes the complexity and bandwidth issues associated with scalable video.

In recent years many methodologies have been proposed for co-designing Field Programmable Gate Array (FPGA) and software systems. In these systems the FPGA is used to accelerate highly parallelisable and time critical parts of the system, while an instruction set processor (ISP) is used for the sequential parts. Existing systems require a specific programming style of the software developer. This makes it virtually impossible to use legacy software. Some systems require a message-passing interface between threads, and allow threads to migrate between software and FPGA [7]. Other systems give access to the hardware using a specific hardware driver and communication libraries [6]. Yet other systems provide a special compiler to enable hardware acceleration [11]. We propose a system where the original Java source code and even the compiled Java bytecode are left unmodified, and the Java Virtual Machine (JVM) is used for handling the communication with the FPGA. [4], [3]

Comparing genetic sequences is a well-known problem in bioinformatics. Newly determined sequences are being compared to known sequences stored in databases in order to investigate biological functions. In recent years the number of available sequences has increased exponentially. Because of this explosion a speedup in the comparison process is highly required. To meet this demand we implemented a dynamic programming algorithm for sequence alignment on reconfigurable hardware. The algorithm we implemented, Smith-Waterman-Gotoh (SWG) has not been implemented in hardware before. We show a speedup factor of 40 in a design that scales well with the size of the available hardware. We also demonstrate the limits of larger hardware for small problems, and project our design on the largest Field Programmable Gate Array (FPGA) available today.

During codesign of a system, one still runs into the impedance mismatch between the software and hardware worlds. This paper identifies the different levels of abstraction of hardware and software as a major culprit of this mismatch. For example, when programming in high-level object-oriented languages like Java, one has disposal of objects, methods, memory management, that facilitates development but these have to be largely abandoned when moving the same functionality into hardware. As a solution, this paper presents a virtual machine, based on the Jikes Research Virtual Machine, that is able to bridge the gap by providing the same capabilities to hardware components as to software components. This seamless integration is achieved by introducing an architecture and protocol that allow reconfigurable hardware and software to communicate with each other in a transparent manner i.e. no component of the design needs to be aware whether other components are implemented in hardware or in software. Further, in this paper we present a novel technique that allows reconfigurable hardware to manage dynamically allocated memory. This is achieved by allowing the hardware to hold references to objects and by modifying the garbage collector of the virtual machine to be aware of these references in hardware. We present benchmark results that show, for four different, well-known garbage collectors and for a wide range of applications, that a hardware-aware garbage collector results in a marginal overhead and is therefore a worthwhile addition to the developer's toolbox.

It is well known that Field Programmable Gate Arrays (FPGAs) can be used to accelerate calculations that take too much time on a Central Processing Unit (CPU). Methodologies have been proposed to reconfigure the FPGA at run time, depending on the needs of the system. The CPU and FPGA generally communicate through message passing, letting the programmer decide exactly which data needs to be passed to the FPGA. As opposed to message passing, we propose a transparent interface between the FPGA and the CPU, which runs a Java Virtual Machine (JVM). Our interface allows regular Java method calls to be intercepted and executed by the FPGA. Conversely, the FPGA will be able to call software methods on the CPU. This portable and transparent interface promotes objectoriented software design for hardware supported applications. Moreover, it allows easy hardware acceleration of existing Java applications.

Reconfigurable computing systems are devices where a CPU controls the system and uses a Field Programmable Gate Array (FPGA) for computationally intensive tasks. Whenever such a task is to be started, the FPGA can be reconfigured and instructed to start the calculation. Such communication is generally based on a message passing interface. As a new alternative we propose a portable and transparent interface between the Java Runtime Environment and a generic FPGA. From the software side, communication with hardware looks like regular method calls, while the hardware can access fields of Java objects, call methods, throw exceptions, etc. We feel this interface can ease hardware support for existing applications and allows development of new hardware supported applications in the object-oriented programming paradigm.