Embedded systems are becoming a more important part of our lives. Students enjoy them on a daily basis, but they cannot imagine they will ever be able to build such systems themselves. We believe that this is due to the dull bottom-up approach that is taken by our science education system. By the time students are allowed to do something fun and interesting with the knowledge they have acquired, they were bored to death by endless hours of abstract science and math classes. We believe that introducing robotics early on in their curriculum can spark their curiosity and revitalize science education.

It has been shown in the past that robots help to bring theoretical concepts into practice, while at the same time increasing the motivation of the students. Despite these benefits, robots are hardly ever integrated in education programs and at the same time students feel that they have the competences nor the infrastructure to build a robot on their own. Therefore the workgroup electronics (WELEK) of Ghent University gives students the opportunity to build a robot by organizing workshops and competitions. Up until now, four competitions were organized in which over 200 students voluntarily participated. This paper describes our approach in the hope that it will inspire other educators to do the same thing. We also measured the effectiveness of our competitions by sending each of the participants a questionnaire. The results confirm that students acquire relevant technical competences by building a robot, learn to work as a team and are challenged to use their creativity.

Application-specific hardware accelerators can significantly improve a system's performance. In a Java-based system, we then have to consider a hybrid architecture that consists of a Java Virtual Machine running on a general-purpose processor connected to the hardware accelerator. In such a hybrid architecture, data communication between the accelerator and the general-purpose processor can incur a significant cost, which may even annihilate the original performance improvement of adding the accelerator. A careful layout of the data in the memory structure is therefore of major importance to maintain the acceleration performance benefits. This article addresses the reduction of the communication cost in a distributed shared memory consisting of the main memory of the processor and the accelerator's local memory, which are unified in the Java heap. Since memory access times are highly nonuniform, a suitable allocation of objects in either main memory or the accelerator's local memory can significantly reduce the communication cost. We propose several techniques for finding the optimal location for each Java object's data, either statically through profiling or dynamically at runtime. We show how we can reduce communication cost by up to 86% for the SPECjvm and DaCapo benchmarks. We also show that the best strategy is application dependent and also depends on the relative cost of remote versus local accesses. For a relative cost higher than 10, a self-learning dynamic approach often results in the best performance.

Smart devices are omnipresent today and the design of these embedded systems requires a multidisciplinary approach. It is important that students in electrical engineering and computer science learn these different aspects of embedded systems design. Our course on Complex Systems Design Methodology presents an overview of embedded systems design with a strong focus on the main concepts, preparing the students for more detailed follow-up courses on specific topics. Imparting the theoretical concepts to the students is not sufficient, however. Hands-on sessions are indispensable for the students to acquire the necessary skills. In this article we present our approach for these hands-on sessions, which is to pose relatively small problems in separate sessions, each focusing on a single design aspect. Five years after the introduction of this new course at Ghent University, we can conclude that students not only like this course, but that their design skills have also improved by our new, aspect-focused, approach.

Hybrid architectures combining the strengths of general-purpose processors with application-specific hardware accelerators can lead to a significant performance improvement. Our hybrid architecture uses a Java Virtual Machine as an abstraction layer to hide the complexity of the hardware/software interface between processor and accelerator from the programmer. The data communication between the accelerator and the processor often incurs a significant cost, which sometimes annihilates the original speedup obtained by the accelerator. This article shows how we minimise this communication cost by dynamically chosing an optimal data layout in the Java heap memory which is distributed over both the accelerator and the processor memory. The proposed self-learning memory allocation strategy finds the optimal location for each Java object's data by means of runtime profiling. The communication cost is effectively reduced by up to 86% for the benchmarks in the DaCapo suite (51% on average).

In many embedded systems, the computational power of an instruction set processor is combined with hardware accelerators. Building such combined systems implies co-design of the software that runs on the processor and the hardware that accelerates the embedded application. During the co-design process, the application is partitioned into a software part (running on the processor) and a hardware part (running on the accelerator). In order to ease the iterative process of partitioning, we introduce a novel design methodology. In our methodology, the interface between hardware and software is transparent to the software designer, and is based on dynamic method interception. Because the interface is transparent and generated automatically, the initial all-software prototype of the system can more easily be refined and partitioned. We show that method interception is inexpensive, and we demonstrate method interception in a real-life application.Using our methodology, embedded systems can be designed fast, reducing time-to-market, while still achieving a high run-time performance.

The new era of multi-core processing challenges software designers to efficiently exploit the parallelism that is now massively available. Programmers have to exchange the conventional sequential programming paradigm for parallel programming: single-threaded designs must be decomposed into dependent, interacting tasks. The Java programming language has built-in thread support and is therefore suitable for the development of parallel software, but programming multi-threaded applications is a tedious task. Therefore we are working on a framework and tool support to alleviate the burden of threads, synchronisation and locking, based on process networks. This paper describes our initial ideas for this new programming model.

According to Moore's law the number of transistors on a single die is doubling every 18 months. During the last decades this evo- lution has lead to an exponential performance increase because processor clock speeds also doubled at the same rate. Due to power limita- tions this clock speed doubling came to an end. Computer architects came up with the idea of multi-core computing: large and complex pro- cessors are replaced by simpler and slimmer cores working together.

As multicore chips scale to higher processor counts, communication between cores becomes more and more important. Indeed, when a single application is split up among multiple cores, which are connected through a relatively slow network, the amount of communication that is required will have an essential effect on performance. Therefore, if the application can be partitioned in such a way that communication between threads is minimised, or that placement on non-uniform networks can be performed with regards to communication, a significant performance boost can be obtained. But to do this effectively, communication streams inside the application must be known. In this paper, we introduce a profiling tool for Java that can measure data flows between methods. It constructs a communication graph, which combines a traditional call graph with data flow information. The overhead of profiling is brought down by a factor of 15 through the use of reservoir sampling. We prove that this can be done with a limited decrease in accuracy. This way, we can quickly estimate communication flows, which forms the critical information that allows an efficient communication-aware parallelisation to be made.

Smart devices are omnipresent today and the design of these embedded systems requires a multidisciplinary approach. It is important that students in electrical engineering and computer science learn all aspects of the design of such systems. Our course on Complex Systems Design Methodology presents an overview of embedded systems design with a strong focus on the main concepts, preparing the students for more detailed follow up courses on specific topics. Imparting the theoretical concepts to the students is not sufficient, however. Hands-on sessions are indispensable for the students to acquire the necessary skills. In this paper we present our approach for these hands-on sessions, which is to pose relatively small problems in separate sessions, each focusing on a single design aspect.

Dynamic hardware generation is a powerful technique that can substantially reduce both the required hardware resources and the time needed to perform a calculation, reflected in an improved functional density. This performance improvement is a result of additional run-time optimizations enabled by the knowledge of values at certain inputs at runtime. However, due to the large overhead conventional hardware generation tools incur, the usability of dynamic hardware generation is limited. We present a dual approach that combines compile-time generation of generic hardware and run-time specialization. This drastically decreases the dynamic generation overhead. Our approach is used for dynamic generation of FIR filters and compared to a static and a conventional dynamic implementation. The experiments clearly show that the dual approach improves the usability of dynamic hardware generation.

Smart devices are omnipresent today and the design of these embedded systems requires a multidisciplinary approach. It is important that students in electrical engineering and computer science learn all aspects of the design of such systems. Our course on Complex Systems Design Methodology presents an overview of embedded systems design with a strong focus on the main concepts, preparing the students for more detailed follow up courses on specific topics. Imparting the theoretical concepts to the students is not sufficient, however. Hands-on sessions are indispensable for the students to acquire the necessary skills. In this paper we present our approach for these hands-on sessions, which is to pose relatively small problems in separate sessions, each focusing on a single design aspect.

The performance of object oriented applications is severely influenced by the access time to the processed data. On a multiprocessor system with distributed shared memory, the average access time can be optimised by allocating the objects in the most appropriate memory. Knowledge of the bandwidths between an object and the different processing elements is important to choose the best allocation. We want to establish dynamic memory allocation on a mixed hardware/software platform. Objects will be moved from one memory to another in order to increase the system performance. Therefore the bandwidth to each object should be measured on the fly, both in hardware and in software. Due to the large number of objects in typical applications and the limited resources, it is not feasible to count data accesses to every object. Only a small number of objects can be tracked. We present a hardware friendly heuristic for dynamically identifying the most accessed objects. Our heuristic also provides estimations of the total number of accesses to each object. Comparison of these estimations with full bandwidth measurements in software shows that the presented heuristic is rather accurate: for some benchmark programs the objects locally responsible for up to 80% of all data accesses are identified. Keywords— profiling, bandwidth, hardware-software codesign, heuristic

The effects of addition of ascorbic and oxalic acids on the atomic absorption signal for lead are explained by a gas-phase thermodynamic equilibrium model. The gas-phase composition of the graphite furnace was determined as samples containing ascorbic or oxalic acid were pyrolyzed. Hydrogen and carbon monoxide were identified as two of the major pyrolysis products. The amounts of these reducing gases, formed in the atomization cycle, varied with the modifier used, the charring temperature employed, and the condition of the surface of the pyrolytically coated graphite tube. The extent of the shift in the appearance temperature showed correlation with variations in concentrations of hydrogen and carbon monoxide produced by pyrolysis. Results for oxalic acid clearly showed that the appearance temperature shifts for lead in pyrolytically coated tubes cannot be explained by a surface reaction mechanism.

The purpose of this paper is to facilitate hardware design. One of the first design decisions is the partitioning of the system in smaller subsystems, which can be implemented on separate hardware and/or software components. Internal communication within components and external communication between different components can be distinguished. Especially external communication is cumbersome, because it determines the requirements for the communication channels in the system. Distinction between internal and external communication is defined by the functional partitioning step which thus has a major impact on the quality of the final design. By estimating communication between functions in advance, we enable a better functional partitioning and therefore improve the communication requirements in the system. As in [4], Java is used in this paper as a specification language for the system, because this language is ideally fit for communication analysis. We present a profiler which measures communication between methods in Java. Our profiler counts the so called consumer-producer relations for each pair of methods. Each consumer-producer relation is defined as a pair of a read operation from and the corresponding write operation to the Java heap memory. The profiling requires a huge increase in execution time. To reduce this overhead, we implement reservoir sampling [11]. This sampling method randomly and uniformly selects a smaller set of read operations to be profiled. The size of this set, i.e. the reservoir, specifies the sampling accuracy. Our approach is evaluated on the SPECjvm98 benchmark suite. The sampling technique reduces the overhead by a factor of 15. Yet accuracy remains within pre-specified limits. Keywords— profiling, communication estimation, sampling and system partitioning