Images consume significant storage and space in both consumer devices and in the cloud. As such, image processing applications impose high energy consumption in loading and accessing the image data in the memory. Fortunately, most image processing applications can tolerate approximate image data storage. In addition, multi-level cell spin-transfer torque MRAM (STT-MRAM) offers unique design opportunities as the image memory: the two bits in the memory cell require asymmetric write current - the soft bit requires much less write current than the hard bit. This paper proposes an approximate image processing scheme that improves system energy efficiency without upsetting image quality requirement of applications. Our design consists of (i) an approximate image storage mechanism that strives to only write the soft bits in MLC STT-MRAM main memory with small write current and (ii) a memory mode controller that determines the approximation of image data and coordinates across precise/approximate memory access modes. Our experimental results with various image processing functionalities demonstrate that our design reduces memory access energy consumption by 53% and 2.3 x with 100% user's satisfaction compared with traditional DRAM-based and MLC phase-change-memory-based main memory, respectively.

Spin-transfer torque magnetic random access memory (STT-RAM) technology has emerged as a potential replacement of SRAM in cache design, especially for building large-scale and energy-efficient last level caches. Compared with singlelevel cell (SLC), multi-level cell (MLC) STT-RAM is expected to double cache capacity and increase system performance. However, the two-step read/write access schemes incur considerable energy consumption and performance degradation. In this paper, we propose two techniques using data compression to optimize MLC STT-RAM cache design. The first technique tries to compress a cache line and fit it into only the soft-bit region of the cells, so that reading or writing this cache line takes only one step which is fast and energy-efficient. We introduce a second technique to increase the cache capacity by enabling the left hard-bit region to store another compressed cache line, which can improve the system performance for memory intensive workloads. The experimental results show that, compared with a conventional MLC STT-RAM last level cache design, our overhead minimized technique reduces the dynamic energy consumption by 38.2% on average with the same system performance, and our capacity augmented technique boosts the system performance by 6.1% with 19.2% dynamic energy saving on average, across the evaluated multi-programmed benchmarks.

Images consume significant storage and space in both consumer devices and in the cloud. As such, image processing applications impose high energy consumption in loading and accessing the image data in the memory. Fortunately, most image processing applications can tolerate approximate image data storage. In addition, multi-level cell spintransfer torque MRAM (STT-MRAM) offers unique design opportunities as the image memory: the two bits in the memory cell require asymmetric write current – the soft bit requires much less write current than the hard bit. This paper proposes an approximate image processing scheme that improves system energy efficiency without upsetting image quality requirement of applications. Our design consists of (i) an approximate image storage mechanism that strives to only write the soft bits in MLC STT-MRAM main memory with small write current and (ii) a memory mode controller that determines the approximation of image data and coordinates across precise/approximate memory access modes. Our experimental results with various image processing functionalities demonstrate that our design reduces memory access energy consumption by 53% and 2.3× with 100% user’s satisfaction compared with traditional DRAM-based and MLC phase-change-memory-based main memory, respectively.

Processing-in-memory (PIM) is a promising solution to address the “memory wall” challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrixvector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360x and the energy consumption by ~895x, across the evaluated machine learning benchmarks.

Process in memory (PIM) is a promising solution to address the “memory wall” issue, and most of the proposed PIM architectures integrate logic with memory. However, as long as the computation is done by logic, it needs to access memory for data. In this work, we propose a novel PIM system, utilizing metal-oxide resistive random access memory (ReRAM) as main memory and also for computation. As an emerging non-volatile memory, ReRAM has been considered as a promising candidate for future memory architecture, thanks to its high density, fast read access, and low leakage power. In addition, it has the capability to represent synaptic weights and execute neural networks with its crossbar architecture. Our proposed design is based on a ReRAM-based main memory system. In the proposed design, a portion of ReRAM crossbar arrays can be configured either as normal memory or to be used for neural computation (hence a morphable PIM structure). We design the required peripheral circuits by computing carefully to minimize the area overhead, and also to provide a hardware-software interface for the developers so that they can easily configure the proposed design for various neural network tasks. We evaluate the proposed design on two sets of benchmarks, and compare it with a CPU-only solution and two neural process unit (NPU) solutions (using NPUs as co-processors and as PIMprocessors through 3D stacking). The experiment results show that the proposed design achieve the best energyefficiency with the highest speedup, which is ∼9000× faster than the CPU-only solution for large neural networks. In addition, it is also a low-overhead PIM solution, with only < 3.8% area overhead compared to the normal ReRAM chips.

The emerging spin-transfer torque magnetic random-access memory (STT-RAM) has attracted a lot of interest from both academia and industry in recent years. It has been considered as a promising replacement of SRAM and DRAM in the cache and memory system design thanks to many advantages, including non-volatility, low leakage power, SRAM comparable read performance and read energy consumption, higher density than SRAM, better scalability than conventional CMOS technologies, and good CMOS compatibility. However, the disadvantages of STT-RAM, such as higher write energy and longer write latency than SRAM, also bring design challenges. This paper introduces state-of-the-art architectural approaches to adopt STT-RAM in the cache and memory system design by taking advantage of the opportunities brought by STT-RAM as well as overcoming the challenges.

With the recent reincarnations of neuromorphic computing comes the promise of a new computing paradigm, with a focus on the design and fabrication of neuromorphic chips. A key challenge in design, however, is that programming such chips is difficult. This paper proposes a systematic methodology with a set of tools to address this challenge. The proposed toolset is called NEUTRAMS (Neural network Transformation, Mapping and Simulation), and includes three key components: a neural network (NN) transformation algorithm, a configurable clock-driven simulator of neuromorphic chips and an optimized runtime tool that maps NNs onto the target hardware for better resource utilization. To address the challenges of hardware constraints on implementing NN models (such as the maximum fan-in/fan-out of a single neuron, limited precision, and various neuron models), the transformation algorithm divides an existing NN into a set of simple network units and retrains each unit iteratively, to transform the original one into its counterpart under such constraints. It can support both spiking neural networks (SNNs) and traditional artificial neural networks (ANNs), including convolutional neural networks (CNNs) and multilayer perceptrons (MLPs) and recurrent neural networks (RNNs). With the combination of these tools, we have explored the hardware/software co-design space of the correlation between network error-rates and hardware constraints and consumptions. Doing so provides insights which can support the design of future neuromorphic architectures. The usefulness of such a toolset has been demonstrated with two different designs: a real Complementary Metal-Oxide-Semiconductor (CMOS) neuromorphic chip for both SNNs and ANNs and a processing-in-memory architecture design for ANNs.

Among the emerging nonvolatile memory (NVM) technologies, some resistive memories, including phase change memory (PCM), spin-transfer torque magnetic random access memory (STT-RAM), and metal-oxide resistive RAM (ReRAM), have been considered as promising replacements of conventional dynamic RAM (DRAM) to build future main memory systems. Main memory databases can benefit from their nice features, such as their low leakage power and nonvolatility, the high density of PCM, the good read performance and low read energy consumption of STT-RAM, and the low cost of ReRAM's crossbar architecture. However, they also have some disadvantages, such as their long write latency, high write energy, and limited lifetime, which bring challenges to database algorithm design for NVM-based memory systems. In this paper, we focus on the design of the ubiquitous B+-tree, aiming to make it NVM-friendly. We present a basic cost model for NVM-based memory systems which distinguishes writes from reads, and propose detailed CPU cost and memory access models for search, insert, and delete operations on a B+-tree. Based on the proposed models, we analyze the CPU costs and memory behaviors of the existing NVM-friendly B+-tree schemes, and find that they suffer from three issues. To address these issues we propose three different schemes. Experimental results show that our schemes can efficiently improve the performance, reduce the memory energy consumption, and extend the lifetime for NVM-based memory systems.

With attractive advantages like high density and low leakage, Spin-Transfer Torque Magnetoresistive RAM (STT-MRAM) is a promising candidate to replace conventional SRAM technology to build large-size and low-power on-chip caches. Multi-level cell (MLC) STT-MRAM, with a higher density, further improves the on-chip cache capacity for chip multiprocessor (CMP) systems. However, the notorious high write energy impedes the adoption of MLC STT-MRAM. In this paper, we focus on minimizing the energy consumption during MLC STT-MRAM write operations. Based on the strong dependency of write energy on data values, a dynamic encoding technique is proposed to map the most frequently appearing data patterns to the most energy-efficient resistance states at runtime. Our experimental results show that, compared with the existing static data mapping scheme, our technique reduces write energy by 12.4% on average and up to 25.4% for a typical MLC STT-MRAM cache.

Emerging nonvolatile memory (NVM), such as spin-transfer torque magnetic Memory (STT-RAM), phase-change memory (PCM), and resistive memory (ReRAM), are widely expected to become the next generation cache and main memory, in order to migrate the “power wall” and overcome the DRAM stability challenge. Previous effort has well explored NVM's feature of ultra-low leakage and high density at various memory hierarchy. Furthermore, challenges such as asymmetric read/write, expensive write operation, and limited lifetime have also been tackled. However, the benefit from NVM's nonvolatility has never been fully exploited. This paper points out the potential benefit by leveraging nonvolatility for architecture design. Two case studies are described. The first one is to leveraging multi-level cell (MLC) STT-RAM for ultra-low overhead local checkpointing. The second one is persistent memory design, which support persistency in NVM based main memory. Potential benefit and design challenge for those two cases are described. Future research topic around exploring NVM's nonvolatility is also discussed.

Process in memory (PIM) is a promising solution to address the “memory wall” issue, and most of the proposed PIM architectures integrate logic with memory. However, as long as the computation is done by logic, it needs to access memory for data. In this work, we propose a novel PIM system, utilizing metal-oxide resistive random access memory (ReRAM) as main memory and also for computation. As an emerging non-volatile memory, ReRAM has been considered as a promising candidate for future memory architecture, thanks to its high density, fast read access, and low leakage power. In addition, it has the capability to represent synaptic weights and execute neural networks with its crossbar architecture. Our proposed design is based on a ReRAM-based main memory system. In the proposed design, a portion of ReRAM crossbar arrays can be configured either as normal memory or to be used for neural computation (hence a morphable PIM structure). We design the required peripheral circuits by computing carefully to minimize the area overhead, and also to provide a hardwaresoftware interface for the developers so that they can easily configure the proposed design for various neural network tasks. We evaluate the proposed design on two sets of benchmarks, and compare it with a CPU-only solution and two neural process unit (NPU) solutions (using NPUs as co-processors and as PIM-processors through 3D stacking). The experiment results show that the proposed design achieve the best energy-efficiency with the highest speedup, which is ∼9000× faster than the CPU-only solution for large neural networks. In addition, it is also a low-overhead PIM solution, with only < 3.8% area overhead compared to the normal ReRAM chips.

The memory and storage system, including processor caches, main memory, and storage, is an important component of various computer systems. The memory hierarchy is becoming a fundamental performance and energy bottleneck, due to the widening gap between the increasing bandwidth and energy demands of modern applications and the limited performance and energy efficiency provided by traditional memory technologies. As a result, computer architects are facing significant challenges in developing high-performance, energy-efficient, and reliable memory hierarchies. New byte-addressable nonvolatile memories (NVMs) are emerging with unique properties that are likely to open doors to novel memory hierarchy designs to tackle the challenges. However, substantial advancements in redesigning the existing memory and storage organizations are needed to realize their full potential. This article reviews recent innovations in rearchitecting the memory and storage system with NVMs, producing high-performance, energy-efficient, and scalable computer designs.

Phase change memory (PCM) is a promising technology for building future large-scale and low-power main memory systems. Main memory databases (MMDBs) can benefit from the high density of PCM. However, its long write latency, high write energy, and limited lifetime, bring challenges to database algorithm design for PCM-based memory systems. In this paper, we focus on making B+-tree PCM-friendly by reducing the write accesses to PCM. We propose three different schemes. Experimental results show that they can efficiently improve the performance, reduce the memory energy consumption, and improve the lifetime for PCM memory.

High reliability, availability, and serviceability are critical for modern large-scale computing systems. As an effective error recovery mechanism, checkpointing has been widely used in such systems for their survival from unexpected failures. The conventional checkpointing schemes, however, are time-consuming due to the limited I/O bandwidth between the DRAM-based main memory and the backup storage. To mitigate the checkpoint overhead, we propose a fast local checkpointing scheme by leveraging Multi-Level Cell (MLC) STT-RAM. We take advantage of the unique features of MLC STT-RAM to accelerate local checkpointing. Our experimental results show that the average performance overhead is less than 1% in a multi-programmed four-core process node with a 1-second local checkpoint interval. The evaluation results also demonstrate that using MLC STT-RAM is an energy-efficient solution.

Brain tumor segmentation is an important technique in computer aided diagnosis. To improve this, it is necessary to use biochemical information provided by magnetic resonance spectroscopy (MRS). An important issue is how to combine the multimodal signals, such as MRS and structure images, and how to use the combined information to make a decision. A data fusion method is proposed in this paper to perform an automatic segmentation of brain tumor. The combinational data of MRS and T2-weighted image should be enhanced by an operation of exponential companding. It consists of five steps: multi-voxel MRS (or CSI) data processing, localization and VOI extraction, data combination, exponential companding, and region growing. Two glioma patients' data provided by Tiantan hospital of China have been used to evaluate our method. Two "ground truth", tumor with edema and tumor only, used for results comparison are manual labels made by neuro radiologists of Tiantan and Nanfang hospitals of China. The segmentation result represents MRS-weighted T2 structure image in tumor region. Its performance is 99% correct detection for tumor only and 98% for tumor with potential edema, and the false detection are 9% and 6% inside VOI, respectively. The proposed method is also a simple information fusion strategy.

In this paper, a post-processing approach of the Hankel Lanczos singular value decomposition (HLSVD) method is proposed to achieve an automatic quantitative analysis of magnetic resonance spectroscopy (MRS). This post processing approach also makes it possible to apply the HLSVD method once to accomplish both the residual water removal and the metabolite quantitation, which reduces a lot of computational time, particularly helpful for the quantitation of multi-voxel MR spectra. The results of the experiments on phantom and in vivo chemical shift imaging (CSI) data have verified the effectiveness of the approach.

This paper presents a glioma modelization method and a regression-like model to create a gradually glioma image (GlioIm). Multimodal signal, images of magnetic resonance imaging (MRI) and in vivo multivoxel MR spectroscopy (MRS) are combined by the regression-like model with spatial resolution registration. This modeling method consists of feature models of glioma such as the signal intensity of MR image and the metabolite changes of MRS, the correlation model noted as metabolites ratio (MetaR) and the combined regression-like model. The estimated GlioIm includes both brain structure and glioma grade information. A nonlinear model is proposed and validated in this paper. The testing data is acquired by Siemens TrioTim (3T) and Syngo MR B15 at Beijing Tiantan hospital (China). The MRS of three glioma patients, two affected by astrocytoma and one by glioma, and the chemical shift imaging (CSI) reference T2 images were considered in our validation experiment. The resulting GlioIms are compared with ground truth provided by neuroradiologists of Tiantan and verified with their pathology report. They report that our method and model are very efficient.

The spectrum of a sinusoid using the Modified Discrete Cosine Transform (MDCT), when separated into an even subspectrum and an odd subspectrum by bin parity, gives rise to a distinctive property-subspectral shapes are independent of the sinusoid phase, which contributes only to scaling. Based on this finding, we propose an Even-Odd (EO) scheme for stereo coding: partitioning the even and odd subspectra separately into subbands to capture the fine spectral structures of sinusoidal and rich tone signals. The scheme reduces the coding noises by 0-20 dB for music signals. When integrated into a MDCT domain KLT-based stereo coder, the scheme boosts subjective listening test (MUSHRA) scores. This coder, called KLT-EO, competes the Parametric Stereo (PS) in quality by a slightly higher bitrate but without the algorithmic delay of 20 ms resulted from the stereo processing.