The growing demand for wide-bandgap (WBG) materials in the microelectronics industry has led to increased investment in medium- and high-voltage power products based on SiC technology. SiC offers an excellent balance between high voltage blocking capability, high temperature operation and high switching frequencies [1]. One key step in preparing high-performance devices is improving the growth process of SiC ingot material by Physical Vapor Transport (PVT). Epitaxial growth occurs through the chemical vapor deposition (CVD) method [2]. However, this method is reported to generate extended defects such as Complex Stacking Faults (formerly referred to as carrots) and Polytype Inclusions (formerly referred to as triangles or comets) and propagate defects pre-existing in the bulk material, such as micropipes (MPs) and threading screw dislocations (TSDs), which have a very high killer ratio in SiC devices [3, 4]. In this work, the KOH molten etching method was used to investigate the nature of the defects that caused device failures; Raman spectroscopy was also employed to identify the spectroscopic correspondence of the peaks of interest.

4H-SiC is a wide-bandgap semiconductor that has become essential for power electronics due to its large bandgap, high critical electric field, and excellent thermal stability. Within the {0001} basal orientation, the two polar surfaces – Si-face and C-face – exhibit distinct behaviours during chemical vapor deposition (CVD) homoepitaxy, with direct implications for device performance and manufacturing. In this work, n -type epitaxial layers were deposited on 150 mm, 4° off-axis Si-face and C-face substrates under identical conditions in a single-wafer hot-wall LP-CVD reactor (T > 1600 °C, P = 3.0 kPa, C/Si = 1.05, silane/propane/ethylene precursors, N₂ doping, HCl additive). Characterization analysis revealed pronounced polarity-dependent differences. AFM analysis showed that C-face epilayers exhibited smoother surfaces and reduced step bunching compared with Si-face layers. Optical and photoluminescence inspections show polarity-dependent defect propagation, with the C-face displaying reduced replication of extended defects under the explored conditions. However, nitrogen incorporation on the C-face orientation was more than 25× higher than Si-face orientation and displayed poor uniformity, highlighting the limited effectiveness of site-competition epitaxy on this orientation. In contrast, the Si-face provides tighter control of doping concentration and lateral uniformity, albeit with higher step bunching and rougher surfaces. These findings emphasize a fundamental trade-off in 4H-SiC homoepitaxy: the C-face offers morphological and structural advantages, while the Si-face ensures superior doping control and process stability. A deeper understanding of these polarity-dependent mechanisms is essential to optimize epitaxial growth strategies and to enable the design of high-performance SiC power devices.

A new design approach on 4H-SiC material is ongoing to improve the electrical performance of devices. As seen in silicon devices, multi-epitaxial growth enhances performance by reducing on-resistance (R on ). However, devices built on SiC face several challenges due to the very low dopant diffusion (e.g. phosphorus and aluminum) and defect evolution during the epitaxial growth. Monitoring defects like prismatic faults, stacking faults, partial dislocations, and micropipes, especially after regrowth, is essential to assess their impact on device performance. Defects with high killer ratio must be closely tracked to understand evolution thereof. In this work, we will show a method for early-stage process characterization and defect root-cause identification through sensitive inspections, effective reviews, and accurate defect classification to detect critical defects in 4H-SiC material when more than one epitaxial step is considered.

The fabrication of high-quality 4H-SiC epitaxial layers for power semiconductor devices involves complex processes including bulk crystal growth, wafer slicing, polishing, and chemical vapor deposition (CVD) epitaxy with precise step-flow control on slightly off-cut Si-face substrates. Despite advances, intrinsic crystallographic defects such as threading dislocations, basal plane dislocations, and stacking faults remain significant challenges, propagating into epitaxial layers and degrading device performance and reliability. This study examines defect types and their impact on 4H-SiC wafers, emphasizing the transition from 150 mm to 200 mm substrates, which introduces increased defect densities and polytype inclusions. Comprehensive defect characterization using advanced microscopy, molten KOH etching, and electrical wafer sorting reveals strong correlations between physical defects—such as micropipes, carrot-like stacking faults, and triangular 3C-SiC inclusions—and device failures, particularly under reliability stress tests like High Temperature Reverse Bias (HTRB). The findings highlight the critical role of substrate quality, epitaxial growth conditions, and defect mapping in improving yield and device robustness. This work underscores the necessity of integrating multi-scale defect inspection and targeted reliability assessments to optimize 4H-SiC power device manufacturing and performance.

The increasing demand for WBG materials like SiC has led STMicroelectronics to expand wafer diameter from 150 mm to 200 mm, enhancing production yield and reducing costs. However, this expansion poses challenges in preserving crystalline quality. This investigation examines the impact of defects on 200 mm wafers, focusing on Total Usable Area (TUA) and electrical performance, particularly in wafers with polytype inclusions and high basal plane dislocation (BPD) density. Although the results for non-standard wafers show a significant reduction in TUA and an increase in electrical failures, the overall distribution of functional and non-functional devices remains stable, indicating process consistency.

The effect of increasing Buffer Layer (BL) thickness on crystal defectivity has been investigated in 4° off-axis 4H-SiC homoepitaxy on 200mm substrates coming from different suppliers. The results, based on optical microscopy and scatter light methods, show a slight increase in morphological defects in the case of a thicker BL with respect to the standard thickness for both suppliers.

3C-SiC films grown on (111) Si substrates exhibit poor crystal quality and experience wafer cracks and bowing preventing access to bulk growth. This work reports innovative Chemical Vapor Deposition (CVD) growth methodology on 4 in. Si substrates which allowed the growth of 230 mm thick layer of (111) 3C-SiC through the melting of the Si substrate in the CVD chamber and the adoption of the resulting free standing 3C-SiC for the growth of bulk (111) 3C-SiC layer under high N fluxes. From the molten KOH etching and subsequent SEM investigation it has been ascertained that with a N2 flux of 1600 sccm there is a significant reduction in the concentration of stacking faults (SFs) from (7.16 +/- 0.04) x 103 cm-1 to (0.4 +/- 0.3) x 103 cm-1. This reduction is consistent with the cross section m-PL response displaying steep and uniform increase in the intensity of the band-edge signal a factor 10 higher on the surface with respect to the equal (100) 3C-SiC grown thickness. Furthermore, the emission attributed to point defects is considerably lower in (111) 3C-SiC. From Scanning Transmission Electron Microscopy (STEM) investigation it appears evident how the typical mechanism valid in (100) growths consisting in the mutual closure of SFs coming from opposing {111} planes that give rise to Lomer and l-shaped dislocations is replaced by a different panorama of evolution. Indeed, it is shown how the SFs shred but do not interrupt each other during growth. Furthermore, dropping in the number of atomic planes composing SFs layers appears to be a key phenomenon leading to both the shrinkage of the number of SF atomic layers as well as to the SF self-closure. High Angle Annular Dark Field-Scanning Transmission Electron Microscopy (HAADF-STEM) attested how the crystal tends to smooth out the lattice mismatch until the SF is suppressed. Because of the foregoing, the mechanisms of evolution of the defects in (111) 3C-SiC revealed in this study, demonstrates how the growth parameters must be matched with the kinetics of the defects in order to endorse (111) 3C-SiC adoption in high performing devices.

This study addresses the poor crystal quality and wafer cracks experienced by 3C-SiC films grown on (111) Si substrates, which prevent access to bulk growth. By employing a novel Chemical Vapor Deposition (CVD) growth method on 4-inch Si substrates, it was possible to grow a layer of (111) 3C-SiC that was 230 μm thick, achieved by melting the Si substrate in the CVD chamber. The resulting free-standing 3C-SiC was then utilized to grow a bulk (111) 3C-SiC layer under high N fluxes. After molten KOH etching, the SEM examination demonstrated a considerable decrease in the density of stacking faults (SFs) with values of (7.16±0.04)×10$^{3}$ cm$^{-1}$ in heteroepitaxial step while SFs density shifts to (0.4±0.3)×10$^{3}$ cm$^{-1}$ when using a N 2 flux of 1600 sccm. The emission linked to point defects is, also, significantly reduced in (111) 3C-SiC with respect to (100) 3C-SiC growth. Scanning Transmission Electron Microscopy (STEM) analysis revealed a different pattern of evolution during (111) growths, where SFs shred but do not interrupt each other during growth. The reduction of SF atomic layers and SF self-closure appears to be the decrease in the number of atomic planes that comprise SF layers. High Angle Annular Dark Field-Scanning Transmission Electron Microscopy (HAADF-STEM) revealed how the crystal works to eliminate lattice mismatch and smooth out the SF until it is removed. These findings highlight the importance of matching growth parameters with defect kinetics to promote the adoption of (111) 3C-SiC in high-performance devices.

The enlargement of 4H-SiC seed size from 150 mm (6 inch) to 200 mm (8 inch) is currently underway and 8 inches SiC substrate is now facing the market to switch the actual 6-inch technology to 8-inch technology. The aim of this work is to evaluate the influence on the epitaxial layer (using an epi growth campaign made of 21 consecutive runs) using substrates coming from different vendors (3 different suppliers adopted). The same epitaxial process and same reactor were adopted to grow all the samples. After the growth campaign, a difference of thickness uniformity between the three substrate suppliers was observed while no difference of doping uniformity was detected.

Growth from vapour/gas/plasma phases is a key process to produce high-quality nanostructures and thin films. The quest for high performances at low cost calls for the development of modelling strategies able to accurately predict growth rates and structure morphology under a variety of process conditions. In the semiconductor nanotechnology, Lattice Kinetic Monte Carlo (LKMC) is considered an advanced approach for simulating selective epitaxy of semiconductors by Chemical Vapor Deposition (CVD). However, state-of-the-art LKMC tools often neglect fundamental aspects such as lattice defects and chemical reactions, both in the vapor phase and around the evolving surface. We present a multiscale workflow for modelling CVD growth and etching processes also accounting for these critical phenomena. We implement it in the open-source KMC super-Lattice (KMCsL) code MulSKIPS , whose peculiar design allows for the generation and evolution of point-like and extended defects in tetrahedrally-bonded materials, such as Si, SiC or SiGe alloys. Gas-phase reactions at the meso-scale are considered by coupling with an external thermodynamic simulator, while surface reactions involving the equilibrium gas species are described by an analytical continuum model. We perform experiments to calibrate and validate the KMCsL model. We then apply the methodology to simulate nanoscale morphology modifications in planar, nanostructured and constrained geometries, unveiling the role of temperature, precursors' pressures, surface coverage and defects kinetics in the CVD process.

The study and evaluation of 4H-SiC 200 mm substrates has revealed an increase of defect density that is generated by the seed expansion. Defects disappeared in 150 mm substrates have to be faced again in 200 mm like polytype inclusions, bar shaped defects and carbon inclusions. They must be suppressed being the root of extended and detrimental defects on epitaxial layer. Raman analysis reveals presence of polytype inclusions (6H or 15R). Also, the monitoring of the TO Raman mode along the whole wafer suggest an additional stress on the material and reduced crystallographic quality. The detection of carbon inclusions suggests a crystallographic quality that has to be improved. An extensive study of the material is in progress to better define the quality of the substrates and provide suitable suggestion to improve the crystal growth.

One setback that hinders the breakthrough of cubic silicon carbide is the lack of suitable seeding material for sublimation growth methods such as PVT. We present the growth of large area cubic silicon carbide material, up to a diameter of 100 mm, with a sublimation growth process called close spaced PVT (CS-PVT). Freestanding 3C‑SiC seeding layers were grown by a homoepitaxial CVD process. Subsequently CS-PVT was used to grow crystals up to a thickness of 1 mm. To prevent backside sublimation a carbon containing layer was applied as protection. Due to the presence of a wafer bow as well as a rough backside of the used seeds additional effort was necessary to apply the coating. After growth no visible curvature was present independent of the grown layer thickness and sample size. Raman spectroscopy was performed on the seeds and grown crystals, showing that the overall stress level of the material was reduced by CS‑PVT.

This work studies the variation of the defects density of in situ doped 3C-SiC layers during heteroepitaxial Chemical Vapour Deposition (CVD). A review on the evolution of defects density as a function of 3C-SiC grown thickness, for different N doping concentrations is offered. The doping range spanned in the experiment suits the realization of power devices.The outcome of this work provides an explanatory picture of the significant drop in stacking faults density by roughly an order of magnitude through the N doping at concentrations of the order of ~2.9×1019 cm-3 during the growth. Conversely, N doping shows to favor the development of dislocation-like defects within the crystalline matrix. However, in few um, the crystal is able to display an effective dislocation closure mechanism, which rapidly recovers crystal quality.

In this work, the effect of high temperature molten KOH wet etching on GaN/AlGaN epilayer has been investigated for different family of dislocations. The high etching temperature (up to 510°C) allows a good definition of the pits, making easy the observation and the counts. Such high temperature will allow a detailed study on the statistical distribution of the dislocations on whole wafer by optical microscope for screw/mixed dislocation. A comparison on dislocation density between AlGaN/GaN structure grown on Si (111) substrate and 4H-SiC substrate has been performed.

In this work the relationship between changes in wafer center bow after thinning process and the wafer morphology has been shown. KOH wet etching allowed the observation and counting of dislocation in 4H-SiC substrate. In deep a correspondence between changes in wafer center bow and the dislocation density of the SiC substrate has been observed. By using a counting software, a relationship with the basal plane dislocation and center bow has also been observed.

This study offers a comprehensive examination of the behavior of 3C-SiC crystals grown on 4° off-axis (100) Si substrates with different off-axis angles along <110> and <100> for N and Al doping, respectively. The investigation takes advantage of molten KOH etching to conduct an in-depth investigation of the average density and size of the SFs inside the crystal for both n- and p-type doped 3C-SiC epitaxial layers. Moreover, 3C-SiC grown on a <100> off-cut substrate was revealed to have a greater concentration of SFs due to the absence of self-annihilation along the plane (-1-10). Considering two different doping ranges suitable for IGBTs and MOSFETs development, the impact of doping and off-angle on the crystal quality, concentration, and length distribution of SFs was then investigated in order to quantify the influence of N and Al incorporation on the structural and optical characteristics of the semiconductor. It turned out that under heavy nitrogen doping (~1019 cm-3), when the dopant concentration grew, the average length of the stacking faults (SFs) expanded while their density dropped.

Despite the promising properties, the problem of cubic silicon carbide (3C-SiC) heteroepitaxy on silicon has not yet been resolved and its use in microelectronics is limited by the presence of extensive defects. In this paper, we used microphotoluminescence (μ-PL), molten KOH etching, and high-resolution scanning transmission electron microscopy (HRSTEM) to investigate the effect of nitrogen doping on the distribution of stacking faults (SFs) and assess how increasing dosages of nitrogen during chemical vapor deposition (CVD) growth inhibits the development of SFs. An innovative angle-resolved SEM observation approach of molten KOH-etched samples resulted in detailed statistics on the density of the different types of defects as a function of the growth thickness of 3C-SiC free-standing samples with varied levels of nitrogen doping. Moreover, we proceeded to shed light on defects revealed by a diamond-shaped pit. In the past, they were conventionally associated with dislocations (Ds) due to what happens in 4H-SiC, where the formation of pits is always linked with the presence of Ds. In this work, the supposed Ds were observed at high magnification (by HRSTEM), demonstrating that principally they are partial dislocations (PDs) that delimit an SF, whose development and propagation are suppressed by the presence of nitrogen. These results were compared with VESTA simulations, which allowed to simulate the 3C-SiC lattice to design two 3C-lattice domains delimited by different types of SFs. In addition, through previous experimental evidence, a preferential impact of nitrogen on the closure of 6H-like SFs was observed as compared to 4H-like SFs.

This work provides a comprehensive investigation of nitrogen and aluminum doping and its consequences for the physical properties of 3C-SiC. Free-standing 3C-SiC heteroepitaxial layers, intentionally doped with nitrogen or aluminum, were grown on Si (100) substrate with different 4° off-axis in a horizontal hot-wall chemical vapor deposition (CVD) reactor. The Si substrate was melted inside the CVD chamber, followed by the growth process. Micro-Raman, photoluminescence (PL) and stacking fault evaluation through molten KOH etching were performed on different doped samples. Then, the role of the doping and of the cut angle on the quality, density and length distribution of the stacking faults was studied, in order to estimate the influence of N and Al incorporation on the morphological and optical properties of the material. In particular, for both types of doping, it was observed that as the dopant concentration increased, the average length of the stacking faults (SFs) increased and their density decreased.

Since the early days of research in the field of the wide band gap semiconductor silicon carbide (SiC), the cubic polytype has been favorable because it exhibits the highest electron mobility. The electronic band gap and electric breakdown are slightly smaller than the hexagonal 4H-SiC. Therefore, the ideal operation range of power electronic devices based on 3C-SiC lies in the mid-voltage range of 400–600 V as it is used in the large application field of electric automotive applications. The current review presents a state-of-the-art overview over the complete processing change from materials growth to device processing.

In this review paper, several new approaches about the 3C-SiC growth are been presented. In fact, despite the long research activity on 3C-SiC, no devices with good electrical characteristics have been obtained due to the high defect density and high level of stress. To overcome these problems, two different approaches have been used in the last years. From one side, several compliance substrates have been used to try to reduce both the defects and stress, while from another side, the first bulk growth has been performed to try to improve the quality of this material with respect to the heteroepitaxial one. From all these studies, a new understanding of the material defects has been obtained, as well as regarding all the interactions between defects and several growth parameters. This new knowledge will be the basis to solve the main issue of the 3C-SiC growth and reach the goal to obtain a material with low defects and low stress that would allow for realizing devices with extremely interesting characteristics.