3C-SiC films grown on (111) Si substrates exhibit poor crystal quality and experience wafer cracks and bowing preventing access to bulk growth. This work reports innovative Chemical Vapor Deposition (CVD) growth methodology on 4 in. Si substrates which allowed the growth of 230 mm thick layer of (111) 3C-SiC through the melting of the Si substrate in the CVD chamber and the adoption of the resulting free standing 3C-SiC for the growth of bulk (111) 3C-SiC layer under high N fluxes. From the molten KOH etching and subsequent SEM investigation it has been ascertained that with a N2 flux of 1600 sccm there is a significant reduction in the concentration of stacking faults (SFs) from (7.16 +/- 0.04) x 103 cm-1 to (0.4 +/- 0.3) x 103 cm-1. This reduction is consistent with the cross section m-PL response displaying steep and uniform increase in the intensity of the band-edge signal a factor 10 higher on the surface with respect to the equal (100) 3C-SiC grown thickness. Furthermore, the emission attributed to point defects is considerably lower in (111) 3C-SiC. From Scanning Transmission Electron Microscopy (STEM) investigation it appears evident how the typical mechanism valid in (100) growths consisting in the mutual closure of SFs coming from opposing {111} planes that give rise to Lomer and l-shaped dislocations is replaced by a different panorama of evolution. Indeed, it is shown how the SFs shred but do not interrupt each other during growth. Furthermore, dropping in the number of atomic planes composing SFs layers appears to be a key phenomenon leading to both the shrinkage of the number of SF atomic layers as well as to the SF self-closure. High Angle Annular Dark Field-Scanning Transmission Electron Microscopy (HAADF-STEM) attested how the crystal tends to smooth out the lattice mismatch until the SF is suppressed. Because of the foregoing, the mechanisms of evolution of the defects in (111) 3C-SiC revealed in this study, demonstrates how the growth parameters must be matched with the kinetics of the defects in order to endorse (111) 3C-SiC adoption in high performing devices.

This study addresses the poor crystal quality and wafer cracks experienced by 3C-SiC films grown on (111) Si substrates, which prevent access to bulk growth. By employing a novel Chemical Vapor Deposition (CVD) growth method on 4-inch Si substrates, it was possible to grow a layer of (111) 3C-SiC that was 230 μm thick, achieved by melting the Si substrate in the CVD chamber. The resulting free-standing 3C-SiC was then utilized to grow a bulk (111) 3C-SiC layer under high N fluxes. After molten KOH etching, the SEM examination demonstrated a considerable decrease in the density of stacking faults (SFs) with values of (7.16±0.04)×10$^{3}$ cm$^{-1}$ in heteroepitaxial step while SFs density shifts to (0.4±0.3)×10$^{3}$ cm$^{-1}$ when using a N 2 flux of 1600 sccm. The emission linked to point defects is, also, significantly reduced in (111) 3C-SiC with respect to (100) 3C-SiC growth. Scanning Transmission Electron Microscopy (STEM) analysis revealed a different pattern of evolution during (111) growths, where SFs shred but do not interrupt each other during growth. The reduction of SF atomic layers and SF self-closure appears to be the decrease in the number of atomic planes that comprise SF layers. High Angle Annular Dark Field-Scanning Transmission Electron Microscopy (HAADF-STEM) revealed how the crystal works to eliminate lattice mismatch and smooth out the SF until it is removed. These findings highlight the importance of matching growth parameters with defect kinetics to promote the adoption of (111) 3C-SiC in high-performance devices.

Driven by the spread of electric vehicles, the market for SiC power devices is expanding so rapidly that many suppliers are struggling to meet the customer's demand both in terms of final devices and raw material, which nowadays consists of SiC wafers with a diameter of 150 mm (6 in.). STMicroelectronics (ST), world leader in the sale of SiC power device, has reacted by starting the in-house production of the next-generation wafers with a diameter of 200 mm (8 in.). This work describes the optimization of the n-type 4H-SiC epilayers on 200 mm substrates performed by ST in collaboration with LPE (R) "an ASM company" (LPE). The density of defects and the thickness and doping uniformity of the epilayers grown on 200 mm substrates are characterized, showing results comparable to the ones obtained for standard 150 mm wafers. Also, the reproducibility of the manufacturing process is improved, resulting in a run-to-run variation of the epilayer's thickness and doping below 2%.

In this paper, we address the unique nature of fully textured, high surface-to-volume 3C-SiC films, as produced by intrinsic growth anisotropy, in turn generated by the high velocity of the stacking fault growth front in two-dimensional (111) platelets. Structural interpretation of high resolution scanning electron microscopy and transmission electron microscopy data is carried out for samples grown in a hot-wall low-pressure chemical vapour deposition reactor with trichlorosilane and ethylene precursors, under suitable deposition conditions. By correlating the morphology and the X-ray diffraction analysis we also point out that twinning along (111) planes is very frequent in such materials, which changes the free-platelet configuration.

This work studies the variation of the defects density of in situ doped 3C-SiC layers during heteroepitaxial Chemical Vapour Deposition (CVD). A review on the evolution of defects density as a function of 3C-SiC grown thickness, for different N doping concentrations is offered. The doping range spanned in the experiment suits the realization of power devices.The outcome of this work provides an explanatory picture of the significant drop in stacking faults density by roughly an order of magnitude through the N doping at concentrations of the order of ~2.9×1019 cm-3 during the growth. Conversely, N doping shows to favor the development of dislocation-like defects within the crystalline matrix. However, in few um, the crystal is able to display an effective dislocation closure mechanism, which rapidly recovers crystal quality.

In this paper, the performance of a new CVD reactor (called PE1O8) designed by LPE and developed in the European project REACTION to process uniform 4H-SiC homoepitaxy on 200 mm substrate is reported. Its tunable multi-zone injection system and new gas delivery configuration ensure the uniform gas distribution throughout the substrate. Excellent thickness and doping uniformity on 200 mm substrates are achieved with run-to-run variation less than 1.4% and 5.6% respectively.

The review on bulk growth of SiC includes a basic overview on the widely used physical vapor transport method for processing of 4H-SiC boules as well as the discussion of three current research topics: (a) Sublimation bulk growth of large area, freestanding cubic SiC, (b) in-situ Visualization of the PVT Process using 2D and 3D X-ray based imaging and (c) prediction of dislocation formation and motion in SiC using a continuum model of dislocation dynamics (CDD).

This study offers a comprehensive examination of the behavior of 3C-SiC crystals grown on 4° off-axis (100) Si substrates with different off-axis angles along <110> and <100> for N and Al doping, respectively. The investigation takes advantage of molten KOH etching to conduct an in-depth investigation of the average density and size of the SFs inside the crystal for both n- and p-type doped 3C-SiC epitaxial layers. Moreover, 3C-SiC grown on a <100> off-cut substrate was revealed to have a greater concentration of SFs due to the absence of self-annihilation along the plane (-1-10). Considering two different doping ranges suitable for IGBTs and MOSFETs development, the impact of doping and off-angle on the crystal quality, concentration, and length distribution of SFs was then investigated in order to quantify the influence of N and Al incorporation on the structural and optical characteristics of the semiconductor. It turned out that under heavy nitrogen doping (~1019 cm-3), when the dopant concentration grew, the average length of the stacking faults (SFs) expanded while their density dropped.

Despite the promising properties, the problem of cubic silicon carbide (3C-SiC) heteroepitaxy on silicon has not yet been resolved and its use in microelectronics is limited by the presence of extensive defects. In this paper, we used microphotoluminescence (μ-PL), molten KOH etching, and high-resolution scanning transmission electron microscopy (HRSTEM) to investigate the effect of nitrogen doping on the distribution of stacking faults (SFs) and assess how increasing dosages of nitrogen during chemical vapor deposition (CVD) growth inhibits the development of SFs. An innovative angle-resolved SEM observation approach of molten KOH-etched samples resulted in detailed statistics on the density of the different types of defects as a function of the growth thickness of 3C-SiC free-standing samples with varied levels of nitrogen doping. Moreover, we proceeded to shed light on defects revealed by a diamond-shaped pit. In the past, they were conventionally associated with dislocations (Ds) due to what happens in 4H-SiC, where the formation of pits is always linked with the presence of Ds. In this work, the supposed Ds were observed at high magnification (by HRSTEM), demonstrating that principally they are partial dislocations (PDs) that delimit an SF, whose development and propagation are suppressed by the presence of nitrogen. These results were compared with VESTA simulations, which allowed to simulate the 3C-SiC lattice to design two 3C-lattice domains delimited by different types of SFs. In addition, through previous experimental evidence, a preferential impact of nitrogen on the closure of 6H-like SFs was observed as compared to 4H-like SFs.

In this paper we report the morphology and the microstructural properties of thick [1 1 1]-oriented 3C-SiC films epitaxially grown on T-shaped Si micropillars. This compliant substrate was designed to release the stress developed in 3C-SiC grown on Si, due to the lattice mismatch and the different thermal expansion coefficients between 3C-SiC and Si. In this way it was possible to have 3C-SiC films as thick as 10 and 16 μm, with small bowing and no cracks. Our study relies on the use of an Electron Microscopy approach and elucidates the structure of the crystallographic defects across the 3C-SiC film, such as stacking faults (SFs), nano-twins and grain boundaries (GBs). After examination of the morphological and structural characteristics of the Si micropillar array, we analyzed the crystallographic properties of the thin 3C-SiC deposit on the Si micropillar sidewalls, since it may have an impact on the upper film. To assess the crystal quality of the 3C-SiC film, we quantified the SF density at the 3C-SiC surface, even estimating semi-quantitatively the depletion of SFs at much larger thickness. Hence, we analyzed the regions where 3C-SiC microcrystals grown on neighboring Si micropillars coalesce and form a continuous layer. We found that the coalescence between adjacent 3C-SiC microcrystals produces twinned regions, which terminate with the formation of GBs. We noticed that SFs may annihilate at the GBs, leading to the SF reduction across the 3C-SiC film. Finally, we observed the closure of the GBs inside the 3C-SiC film, thus improving the crystal quality of its surface. This work endorses the use of Si micropillars as compliant substrate to grow thick [1 1 1]-oriented 3C-SiC films with good crystal quality and is preliminary to the exploitation of 3C-SiC for high performing microelectronic devices.

In recent years, the power electronics industry based on silicon carbide (SiC) has rapidly expanded, but suppliers are struggling to meet the market demand both for final devices and for the starting raw material, which nowadays consists of SiC wafers with a diameter of 150 mm (6 inches). For this reason, the top industrial players in the field of SiC power electronics are starting the development of next-generation wafers with a diameter of 200 mm (8 inches). This work describes the recent achievements in the implementation of the world's first industrial pilot line to produce power devices based on 200 mm SiC wafers. In particular, the crystal growth of the 200 mm SiC boules, the slicing and polishing of the wafers, the deposition of the epitaxial layer, and the first tests in the pilot lines are presented.

Stacking fault annihilation mechanism in 3C-SiC epitaxially grown on Si(001) is studied by molecular dynamics simulations and its implications for improvement of 3C-SiC characteristics are provided.

This work provides a comprehensive investigation of nitrogen and aluminum doping and its consequences for the physical properties of 3C-SiC. Free-standing 3C-SiC heteroepitaxial layers, intentionally doped with nitrogen or aluminum, were grown on Si (100) substrate with different 4° off-axis in a horizontal hot-wall chemical vapor deposition (CVD) reactor. The Si substrate was melted inside the CVD chamber, followed by the growth process. Micro-Raman, photoluminescence (PL) and stacking fault evaluation through molten KOH etching were performed on different doped samples. Then, the role of the doping and of the cut angle on the quality, density and length distribution of the stacking faults was studied, in order to estimate the influence of N and Al incorporation on the morphological and optical properties of the material. In particular, for both types of doping, it was observed that as the dopant concentration increased, the average length of the stacking faults (SFs) increased and their density decreased.

In this review paper, several new approaches about the 3C-SiC growth are been presented. In fact, despite the long research activity on 3C-SiC, no devices with good electrical characteristics have been obtained due to the high defect density and high level of stress. To overcome these problems, two different approaches have been used in the last years. From one side, several compliance substrates have been used to try to reduce both the defects and stress, while from another side, the first bulk growth has been performed to try to improve the quality of this material with respect to the heteroepitaxial one. From all these studies, a new understanding of the material defects has been obtained, as well as regarding all the interactions between defects and several growth parameters. This new knowledge will be the basis to solve the main issue of the 3C-SiC growth and reach the goal to obtain a material with low defects and low stress that would allow for realizing devices with extremely interesting characteristics.

3C-SiC is a promising material for low-voltage power electronic devices but its growth is still challenging. Heteroepitaxy of 3C-SiC on Si micrometer-sized pillars is regarded as a viable method to achieve high crystalline quality, minimizing the effects of lattice and thermal expansion mismatch. Three-dimensional micro-crystals with sharply-faceted profiles are obtained, eventually touching with each other to form a continuous layer, suspended on the underlying pillars. By comparing experimental data and simulation results obtained by a phase-field growth model, here we demonstrate that the evolution of the crystal morphology occurs in a kinetic regime, dominated by the different incorporation times on the crystal facets. These microscopic parameters, effective to characterize the out-of-equilibrium growth process, are estimated by a best-fitting procedure, matching simulation profiles to the experimental one at different deposition stages. Then, simulations are exploited to inspect the role of a different pillar geometry and template effects are recognized. Finally, coalescence of closely spaced crystals ordered into an hexagonal array is investigated. Two possible alignments of the pattern are compared and the most convenient arrangement is evaluated.

We present an investigation of the structural quality of arrays of 3C-SiC micropillars and microridges grown epitaxially on deeply etched Si(0 0 1) substrates offcut towards [1 1 0]. Using high resolution X-ray diffraction with reciprocal space mapping and optical as well as scanning electron microscopy, we obtain information about the stacking fault (SF) formation in different crystallographic directions. The SF density is strongly correlated with the microcrystal size and orientation and a reduction of the SF density is found in the [1 1 1] and [1-1 1] directions. No variation of the average SF size was detected for varying SiC microcrystal size and shape.

The exceptionally large thermal strain in few-micrometers-thick 3C-SiC films on Si(111), causing severe wafer bending and cracking, is demonstrated to be elastically quenched by substrate patterning in finite arrays of Si micro-pillars, sufficiently large in aspect ratio to allow for lateral pillar tilting, both by simulations and by preliminary experiments. In suspended SiC patches, the mechanical problem is addressed by finite element method: both the strain relaxation and the wafer curvature are calculated at different pillar height, array size, and film thickness. Patches as large as required by power electronic devices (500–1000 μm in size) show a remarkable residual strain in the central area, unless the pillar aspect ratio is made sufficiently large to allow peripheral pillars to accommodate the full film retraction. A sublinear relationship between the pillar aspect ratio and the patch size, guaranteeing a minimal curvature radius, as required for wafer processing and micro-crack prevention, is shown to be valid for any heteroepitaxial system.

The cubic polytype of SiC (3C-SiC) is the only one that can be grown on silicon substrate with the thickness required for targeted applications. Possibility to grow such layers has remained for a long period a real advantage in terms of scalability. Even the relatively narrow band-gap of 3C-SiC (2.3eV), which is often regarded as detrimental in comparison with other polytypes, can in fact be an advantage. However, the crystalline quality of 3C-SiC on silicon has to be improved in order to benefit from the intrinsic 3C-SiC properties. In this project new approaches for the reduction of defects will be used and new compliance substrates that can help to reduce the stress and the defect density at the same time will be explored. Numerical simulations will be applied to optimize growth conditions and reduce stress in the material. The structure of the final devices will be simulated using the appropriated numerical tools where new numerical model will be introduced to take into account the properties of the new material. Thanks to these simulations tools and the new material with low defect density, several devices that can work at high power and with low power consumption will be realized within the project.

High performance GaN-based high electron mobility transistors (HEMTs) on SiC require low-miscut (~0.45°), resistive substrates, which are very expensive. A cost-effective solution is to use resistive SiC template i.e., grow a thick resistive SiC epitaxial layer on cheap, conductive SiC substrate. However, this approach requires much higher miscut (2–8°). In the present work we show a lateral patterning technology capable to locally decrease the high miscut of the resistive SiC template, down to a level acceptable for GaN epitaxy. On such patterned SiC templates we grew smooth AlGaN/GaN structures. The maximum width of flat regions available for device fabrication was nearly 100 µm. In these flat regions AlGaN-based HEMTs were fabricated and characterized.