This paper investigates the implementation of sub-resolution assist features (SRAFs) in high performance logic designs for the poly-gate conductor level. We will discuss the concepts used for SRAF rule generation, SRAF data preparation and what we term "binary" optical proximity correction (OPC) to prevent catastrophic line-width problems. Lithographic process window (PW) data obtained with SRAFs will be compared to PW data obtained without SRAF. SRAM cells are shown printed with annular illumination and SRAFs, for both the 130 nm and 100 nm logic nodes as defined by the International Technology Roadmap for Semiconductors (ITRS). This study includes a comparison of the experimental results of SRAMs printed from designs corrected with rule-based OPC to those printed from designs corrected with model-based OPC.

This paper presents a high performance 90 nm generation SOI CMOS logic technology. Leveraging unique SOI technology features, aggressive ground rules and a tungsten local interconnect rendered the smallest 6T SRAM cell reported to date with a cell area of 0.992 /spl mu/m/sup 2/. In the front-end of line (FEOL), the implementation of super-halo design concepts on SOI substrates with a silicon thickness of 45 nm and an ultra-thin heavily nitrided gate dielectric resulted in highest performance devices. The backend of the line (BEOL) for this technology consists of damascene local interconnect followed by up to 10 levels of hierarchical Cu metallization. It utilizes SiLK/spl trade/ low-K dielectric material with a multilayer hard mask stack.

This paper presents data obtained in developing a process using 193 nm lithography and the RELACS contact hole shrink technique. For the line/space levels, process windows showing resist performance using chrome on glass masks are presented. Data showing feature size linearity and the requirements for optical proximity correction (OPC) are presented. Some of the OPC trends observed are discussed and compared to results obtained using 248 nm lithography. Image shortening data also compares the results obtained in 193 and 248 lithography. Etch results for the new 193 resists are given and show the etch resistance of this relatively new class of photoresist materials. For contact hole and via levels, results using 193 lithography and COG masks show the importance of the mask error enhancement factor (MEEF), print bias and resolution. Due to the relative immaturity and performance of contact hole resists for 193 lithography, Clariant's RELACS process was investigated with 248 nm resists. In this process contact holes are printed larger than required and then reduced to the desired size by a chemical shrink process. Results obtained with 248 lithography using state of the art resists and phase shift masks are discussed. It was found that 140 nm contact holes with at least 0.5 micrometer depth of focus could be obtained. Cross sections and process windows are shown.

Silicon-containing bilayer thin-film imaging resists versus single layer resists for a variety of different mask types, from both a focus-expose window, etch selectivity, and process integration perspective are examined. Comparable lithographic performance is found for 248 nm single layer and bilayer resists for several mask levels including: a 135 run dense contact/deep trench mask level, a 150 and 125 nm equal line space mask printed over trench topography, and dual damascene mask levels with both vias and line levels. The bilayer scheme is shown to significantly relax the dielectric to resist etch selectivity constraint for the case of a dense contact or trench hardmask level, where high aspect ratio dielectric features are required. Only a bilayer resist scheme in combination with a transfer etch process enables the line/space pattern transfer from the imaging layer to the bottom of a trench with a combined aspect ratio > 10. When the single layer resist depth of focus window is limited by both the topography and variations in the underlying dielectric stack thickness, as is the case for the dual damascene via and line levels, bilayer resist is shown to be a practical alternative.

The line-width variation of a 193 nm lithographic process utilizing a 0.60 NA scanner and a binary reticle is compared to that of a 248 nm lithographic processes utilizing a 0.68 NA scanner and a variety of reticle technologies. These include binary, attenuated PSM with assist features and alternating PSM reticles. Despite the fact that the 193 nm tool has a lower NA and that the data was generated using a binary reticle, the 193 nm lithographic process allows for the line-width values to be pushed lower than previously achieved with 248 nm lithographic processes. The 3-sigma values from 4000 electrical line-width measurements per wafer (160 measurements per 25*25 mm field, 25 fields per wafer) were calculated for different mask features. The 193 nm process was capable of reaching line-widths needed for future generations of advance logic chips. Compared to the 193 nm process utilizing a binary reticle, only the 248 nm processes utilizing either an attenuated PSM with assist features or an alternating PSM reticle had similarly low line-width variation. The 248 nm processes utilizing a binary reticle had higher line-width variation even at larger poly gate conductor line-widths.

This paper describes a 1.2V high performance 0.13 /spl mu/m generation SOI technology. Aggressive ground-rules and a tungsten damascene local interconnect render the densest 6T SRAM reported to date with a cell area of 2.16 /spl mu/m/sup 2/. This is accomplished with 248nm lithography, using optical proximity correction and resolution enhancement techniques on all critical levels. Interconnect performance requirements are achieved by using up to 8 levels of Cu wiring and an advanced low-k interlevel dielectric.

The problem of image shortening is well known in semiconductor lithography. As rectangular features decrease in width, the length of the feature will print smaller than the mask image length. This problem places a constraint upon overall device design because space must be allowed for line extensions and/or adding to the side of features. Making corrections for image shortening requires mask redesign, which increases the time and cost of new product development.

Many semiconductor chip designs require precise simultaneous control of both the width and length of asymmetric features. Line shortening due to optical, resist processing, and mask effects cause the process windows for width and length to diverge. Typically differential mask biasing has been used to maximize the common process window for both axes. As we enter the gigabit era limitations in grid size and mask write times may become significant restrictions to meeting required device tolerances with that approach.Simulations of aerial image and resist processing using SPLAT(1) and LEOPOLD2,3 indicate that for a given mask there is considerable latitude to adjust the length of features without a significant loss of process window. An experimental design matrix was used to verify the simulation results and develop a regression model of pupil fill, numerical aperture, and resist diffusion effects. This model was then applied to optimize the processing conditions for several product masks. This technique is particularly useful early in the development cycle when mask to mask repeatability is poor and lead times are long. It may also be used to fine tune image sizes in manufacturing.

Typically all defects found on a photomask are repaired, despite the fact that many of the defects would not cause problems on the wafer. Ideally, if the lithographic process does not image the defect onto the wafer in such a way as to adversely affect the performance of the device, then the mask maker should not be required to repair the defect - saving time and money. It is difficult to classify defects in this manner, however, as the impact of the defect depends on various factors, including: lithography process parameters, proximity of defect to a critical feature, feature type and the size, shape, phase and transmission of the defect. These effects are further complicated by shrinking critical feature sizes and the use of resolution enhancement techniques, such as PSM and OPC.To address this problem, a new method of determining the printability of defects on all types of photomasks was developed. This method involves characterizing the aerial image of the defect and assigning an equivalent mask CD error to the defect. The equivalent CD error is then compared to the mask CD error specification to determine if the defect should be repaired. This methodology ties the mask defect specification directly to the device performance specifications and accounts for the multitude of factors that influence the defect printability in a real lithography process. This technique has been used to evaluate attenuated and alternating PSM.

Magnification of mask dimensional error is examined and quantified in terms of the mask error factor (MEF) for Line and hole patterns on three types of masks: chrome-on-glass (COG), attenuated phase-shifting mask (PSM) and alternating PSM. The MEF is unity for large features, but increases rapidly when the critical dimension (CD) is less than 0.5 lambda/NA for line-space patterns and 0.75 lambda/NA for contacts. In general dark-field spaces exhibit higher sensitivity to mask dimensional error than light-field lines. Sensitivity of attenuated PSMs is similar to COG masks, even for applications in which attenuated PSMs provide benefits in process latitude. Alternating PSMs have the lowest MEF values. Although the MEF has only a slight dependence on feature nesting for contacts, dense lines and spaces exhibit markedly higher MEF values than isolated features. The MEF of a 0.35 lambda/NA isolated line is 1.6 whereas that of a dense line of the same dimension is 4.3! Annular illumination is effective in reducing the mask error sensitivity of dense lines. Dose variation causes changes in the MEF of contacts but has little effect on line-space features; focus error degrades (increases the value of) the MEF of both pattern types. A high diffusion and low contrast photoresist process also worsens the MEF Consequences of mask CD error amplification include tightening of mask specification, design grid reduction, shift in optimal mask bias and enhanced defect printability.

The traditional lithographic approach employed by the semiconductor industry has been to pursue use of advanced prototype optical exposure tools and resists. The benefits of doing so have been: (1) The lithographic process that is used in development more closely resembles the process that will in fact be used to manufacture the chip. (2) The cost of low K1 imaging (phase-masks, off-axis illumination, and surface imaging resist) can be avoided. However with the introduction of 1Gb-dynamic random access memory (DRAM) development, a paradigm shift is being experienced within the optical lithographic community. With 1Gb-DRAMs, the minimum feature size falls irreversibly below the optical wavelength used to image the feature. Such a situation will make low K1 factor imaging unavoidable. With 175 nm groundrules typical for first generation 1G-DRAMs, K1 factors near 0.4 will be common with 0.5 as an upper limit on advanced systems currently in development irrespective of optical wavelength. This paper will cover the selection process, experimental data, and problems encountered in defining and integrating the lithographic process used to support the critical mask levels on 1Gb-DRAM development. Factors considered include: resist, masks, and illuminations via both simulation and experiment. The simulations were conducted with both internal and externally developed software. The experimental data to be reviewed was generated using an experimental 0.6 NA KrF step and scan system provided by Nikon. The resist used is commercially available from the Shipley corporation.

Introduction Phase-shifting masks (PSMs) [1][2] and modified illumination techniques [3] have shown promise in improving the resolution and process latitude of lithography. For 1 Gb-DRAM application, these techniques are essential because printing 175 nm features is pushing the limits of even high numerical aperture (NA) deep-UV exposure systems, and wavelength reduction is not an alternative until the availability of 193 nm exposure systems around the turn of the century. This paper explores the application of attenuated PSM [2] and alternating PSM [l], as well as annular illumination [3] in the optimization of lithographic performance at the 175 nm groundrule. Lithographic simulation including the effects of photoresist processing [4] was used to identify optimal conditions for critical levels of a 1 Gb-DRAM cell design [5], and improvement in performance was quantified experimentally. Process Optimization To ensure reliability of the 1 Gb cell requires the control of feature edge placement to within 17.5nm (&lo%). Based on this criterion, exposure-defocus analyses [6] were performed on the viable resolution enhancement techniques, and their relative merits are quantified in terms of depth-of-focus (DOF) with 10% exposure dose variation. Simulation is performed using SPLAT [7] and an internal IBM program LEOPOLD which models the important effects of photoresist processing. Fig. 1 shows the mask and illumination techniques examined. For each critical level, the three approaches which give the largest DOF (at 10% exposure latitude) are listed in Table 1 together with the design layout. The latitude obtained with conventional chromium (COG) mask and standard illumination is also included for reference. In general, annular illumination and alternating PSM are strong candidates for grating-like levels, while attenuated PSM provides the most benefit for contact levels. It is of interest to note the use of negative resist for the active area (AA) level. Fig. 2 illustrates the improvement in image integrity with resolution enhancement techniques for the AA level. The contours represent aerial image intensity in steps of 0.1 normalized to the clear field intensity. For a COG mask with standard illumination, the intensity contours are sparse in both the width (horizontal) and length (vertical) directions, indicating poor image quality and resulting in a DOF of only 0.4 pm. For an attenuated PSM with annular illumination, the intensity contours are denser, resulting in an improved DOF of 1.2 pm. With an alternating PSM at a reduced partial coherence factor of 0.3, the intensity gradient is especially steep at the ends of the feature due to the effects of phase-shifting. This manifests as a better DOF of 1.4 pm and improved line-end shortening behavior: the length is only biased at lOOnm as opposed to 150nm on the COG and attenuated PSM. Mask imperfection limits and in some cases obliterates the benefits of PSMs. Fig. 3 shows the DOF for a 225nm bitline contact (CB) with different types of mask imperfection. With an ideal attenuated PSM, the best DOF exceeds 2.0 pm. This DOF decreases to 1.4 pm with f5 nm of mask critical dimension (CD) error. With the addition of 410.5% transmission and f 5 " phase variation, the DOF is further degraded to 0.4 pm, virtually indistinguishable from that of a COG mask with f 5 nm of mask CD error. Thus, transmission and phase control of the attenuated PSM must be better than f0.5% and ~ t 5 ' respectively for it to have any advantage over COG masks on the CB level. Experimental Results Biased COG and PSM reticles were fabricated for the deep trench (DT), AA, gate conductor (GC), bitline (MO), and CB levels. The reticles were exposed on a Nikon deep-UV step-andscan system (A = 248nm, N A = 0.6, CT = 0.6). For annular illumination, the inner and outer radii correspond respectively to U = 0.5 and (r = 0.75. The positive [8] and negative [9] resists are 0.6 pm and 0.5 pm thick, respectively. Table 2 summarizes the DOF (at 10% EL) for various levels determined from top-down scanning electron micrograph (SEM) measurement. The use of resolution enhancement techniques improve the process latitude of all levels. Of particular interest is the AA level, which calls for the use of negative photoresist. Fig. 4 shows the top-down SEMs of AA patterns exposed with annular illumination and attenuated PSM in negative resist over a 1 .O pm focus range. The DOF is approximately 0.8 pm between the focus at which the pattern loses integrity (-1.2 pm) and the focus at which stringers are observed (-0.2 pm). In a DRAM chip, it is important to print both the array and peripheral patterns. In some cases, the use of resolution enhancement techniques improves the process latitude of array features but degrades the integrity of peripheral patterns. For example, while the use of annular illumination in the MO level improves the grating-like array patterns, the end line of the peripheral feature shows signs of necking and bridging as shown by the SEM in Fig. 5. This problem can be remedied by biasing of the outer line and modifying the etch process. Conclusion Level-specific lithography optimization for a 1 Gb DRAM cell has been demonstrated based on simulation and experimental studies. Results indicate that the optimal lithographic approach is strongly dependent on feature pattern. The use of resolution enhancement techniques for process improvement within the array may lead to modifications of design rule for peripheral features. PSM imperfection due to fabrication may also limit the benefits of such masks. References [I] M. Leuenson, N Viawanatha", and R Simpson, "Improving Resolution ~n Photolithography with a Phase-shifting Mask." IEEE Trans. Electron Devices, voI ED-29, no. 12, pp. 1812-1846, December 1982 (21 B Lin. "The Attenuated Phase-shifting Maek," Solid State Tech., voi 35, no. 1 . pp. 43-47. January 1992 [3] K Kamon. T. Miyamoto, Y. Myoi, H Tanaka, and M Tanaka. "Photolithography System Using Modified Illumination," Jpn. J . Appl. Phys , YOI 32. no 1 A . pp. 239243, 1993 [4] T . Brunner and R . Ferguson, "Simple m o d e l s for resist processing effects," Solid State Tech., p p . 95-103. June 1996. 151 the 1Gb cell 1 s an extension of the cell in L . Nesbrt, et a i . , " 0 . 6 w m 2 5 6 M b trench DRAM cell with self-aligned BuriEd STrap (BEST) ," IEDM Technical Digest, pp 627630, 1993. [6] B Lin, "Partially Coherent Im=ging ~n Two-dimensions and Theoretical Llmits of Projection Printing in Microfabrication." IEEE Trans. Electron Devices. vol. ED-27, p. 931 , 1980 [7] K . Toh, "Two-dimensional Images with Effects of Lens Aberrations jn Optical Lithography." M. S. Thesis, Memorandum No UCB/ERL M88/30, University of Callfornia, Berkeley, May 1988 [SI W . Conley, e t al. "The Lithographic Performance of an Environmentally Stable Chemically Amplified Photoresist (ESCAP) ," Proc SPIE, "01 2724, pp 34-60. 1996. 191 W. Conley, et al , "Negative DUV Photoresist for 1 6 M b DRAM Production and Future Generations," Proc SPIE, YOI 1925. pp 120-132, 1993

Silicone rubber may very conveniently be used to cast a mold from a variety of surface-relief optical components and surfaces. From this it is very simple to cast replicas in epoxy resin. The method owes its success in a large part to the flexibility of the rubber mold which eases the process of separation both from the master and from the final replica. However, the flexibility also gives rise to distortions in the final replica. This paper reports preliminary work to quantify these distortions under various casting conditions.