Printing small vias with tight pitches is becoming very challenging and consequently, different techniques are explored to achieve a robust and stable process. These techniques include reverse tone imaging (RTI) process, source optimization, mask transmission (attenuated Phase Shift Masks (attnPSM) versus binary thin OMOG masks), three-dimensional mask effects models, and SRAF printing models. Simulations of NILS, MEEF, DoF and process variability (PV) band width across a wide range of patterns are used to compare these different techniques in addition to the experimental process window. The results show that the most significant benefits can be gained by using attnPSM masks in conjunction with source optimization and RTI process. However, this improvement alone is not enough; every facet of the computational lithography and process must be finely tuned to produce sufficient imaging quality. As technology continues to shrink, Electromagnetic Field (EMF)-induced errors limit the scalability of this process and we will discuss the need for advanced techniques to suppress and correct for them.

The objective of this work is to describe the advances in 193nm photoresists using negative tone developer and key challenges associated with 20nm and beyond technology nodes. Unlike positive tone resists which use protected polymer as the etch block, negative tone developer resists must adhere to a substrate with a deprotected polymer matrix; this poses adhesion and bonding challenges for this new patterning technology. This problem can be addressed when these photo resists are coated on anti-reflective coatings with plentiful silicon in them (SiARC), which are specifically tailored for compatibility with the solvent developing resist. We characterized these modified SiARC materials and found improvement in pattern collapse thru-pitches down to 100nm. Fundamental studies were carried out to understand the interactions between the resist materials and the developers. Different types of developers were evaluated and the best candidate was down selected for contact holes and line space applications. The negative tone developer proximity behavior has been investigated through optical proximity correction (OPC) verification. The defectivity through wafer has been driven down from over 1000 adders/wafer to less than 100 adders/wafer by optimizing the develop process. Electric yield test has been conducted and compared between positive tone and negative tone developer strategies. In addition, we have done extensive experimental work to reduce negative tone developer volume per wafer to bring cost of ownership (CoO) to a value that is equal or even lower than that of positive tone CoO.

As 193-nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28-nm technology nodes has been greatly facilitated by the just-intime introduction of new process enablers that allow the support of flexible foundry-oriented ground rules alongside high-performance technology, without inhibiting migration to a single-pass patterning process. The incorporation of device-based performance metrics, along with rigorous patterning and structural variability studies, was critical in the evaluation of material innovation for improved resolution and CD shrink. Additionally, novel design changes for single patterning incorporating mask optimization efforts, along with new capability in data preparation, were assessed to allow for minimal impact of implementation of a single patterning contact process late in the 32-nm and 28-nm development cycles. In summary, this paper provides a comprehensive study of what it takes to turn a contact-level double-patterning process into a single-patterning process consisting of design and data manipulation, as well as wafer manufacturing aspects, together with many results. (C) 2012 Society of Photo-Optical Instrumentation Engineers (SPIE). [DOI: 10.1117/1.JMM.11.1.013010]

Silicon-containing bilayer thin-film imaging resists versus single layer resists for a variety of different mask types, from both a focus-expose window, etch selectivity, and process integration perspective are examined. Comparable lithographic performance is found for 248 nm single layer and bilayer resists for several mask levels including: a 135 run dense contact/deep trench mask level, a 150 and 125 nm equal line space mask printed over trench topography, and dual damascene mask levels with both vias and line levels. The bilayer scheme is shown to significantly relax the dielectric to resist etch selectivity constraint for the case of a dense contact or trench hardmask level, where high aspect ratio dielectric features are required. Only a bilayer resist scheme in combination with a transfer etch process enables the line/space pattern transfer from the imaging layer to the bottom of a trench with a combined aspect ratio > 10. When the single layer resist depth of focus window is limited by both the topography and variations in the underlying dielectric stack thickness, as is the case for the dual damascene via and line levels, bilayer resist is shown to be a practical alternative.

Optical Proximity Correction has emerged as an industry standard technique to reproduce the desired shapes on wafers as pattern dimensions are approaching the optical resolution limits. However secondary effects, if not properly controlled, may impede successful application of this technique. In order to better assess these factors we have divided the overall pattern formation process into several obvious components: The illumination system, mask, projection optics, resist system and finally etch processes. Each one of these components influences the optical proximity effects observed in the final pattern. The dependence of optical proximity corrections on the type of illumination is fairly well known and will only be touched on. Variations in the mask manufacturing process such as deviations of the mask critical dimension from its nominal value will be discussed. The type of e-beam exposure tool used to write the mask was found to have profound impact on optical proximity correction and therefore specifying the type of mask writing tool and sometimes even its writing mode to ensure reproducible results is required. Lens aberrations in the optical exposure tool and their impact were studied using aerial image simulations. Examples of optical proximity curves from different first generation tools show significant differences even between tools of the same type. Resist effects and the variations induced by modifying etch processes were investigated emphasizing that a fairly detailed control of the overall pattern formation process is necessary to successfully implement any OPC approach.

Patterning sub-150 mn features in dielectric stacks using single layer resist processes in conjunction with organic antireflective coatings (ARCs) is becoming very difficult. Typical organic ARC-open etch processes suffer from poor ARC-to-resist selectivities (similar to0.7), and are accompanied by critical dimension (CD) losses. The resist remaining is often not sufficient to prevent artifacts such as substrate 'microcrevicing' during subsequent etches. PECVD-deposited titanium nitride and silicon oxynitride films have been investigated as ARC layers but their basic nature has caused residue formation at the resist/ARC interface.We have developed a PECVD-deposited material, TERA (Tunable Etch-Resistant ARC) that acts as an ARC at 248 nm and 193 nm wavelengths and provides excellent etch selectivity to resist surpassing those attained with organic ARCs(+). In addition, this material demonstrates excellent hard mask properties for subsequent dielectric etch steps. The optical properties of these films can be easily tuned to minimize substrate reflectance at either imaging wavelength by controlling the precursor composition and deposition conditions. The films are compatible with 248 run and 193 mn resists - no footing, undercut or residue is observed during patterning. The films can be etched selectively to resist (selectivity similar to2.5) that translates to less resist consumption during the ARC-open etch. Compared to resists, TERA demonstrates better etch resistance while patterning dielectric stacks - the silicon oxide-to-TERA selectivity exceeds 8.In this paper, the excellent optical tunability and substrate reflectivity control achieved with TERA are discussed. Clean lithography using 248 nm, 193 mn and e-beam resists is shown. The etch characteristics of TERA in fluorocarbon and halogen-based plasma chemistries are discussed. Finally, the formation of 135 nm and 120 nm deep trench patterns in thick dielectric stacks using TERA in conjunction with commercial 248 nm and 193 nm resists, respectively is demonstrated. The extendibility of this approach to pattern silicon without roughening or 'microcrevicing' using sub-200 nm thick resists is motivated.

A special class of post-development defects, referred as Circular Surface Defects (CSDs), has been reported Up to now, no resist is immune to CSD printing including eight commercial KrF resists (from two vendors) and six early samples of ArF resists (from five vendors). An extensive study on the CSDs was conducted on a KrF Resist A, in term of its origin, formation and removal mechanism. Photoacid generators (PAGs) are proved to be a primary contributor to the CSDs. The origin of CSDs is believed to be PAG aggregation along with other hydrophobic components, resulting in formation of microemulsions in the developer. The aggregates have limited solubility in aqueous base developer, and could redeposit on the wafer surface during development.We propose one major defect removal mechanism, or "Stripping" mechanism. This mechanism is related to resist film thickness loss, which aids in stripping potential defects from the resist surface, or reducing the probability of defect deposition.

The traditional lithographic approach employed by the semiconductor industry has been to pursue use of advanced prototype optical exposure tools and resists. The benefits of doing so have been: (1) The lithographic process that is used in development more closely resembles the process that will in fact be used to manufacture the chip. (2) The cost of low K1 imaging (phase-masks, off-axis illumination, and surface imaging resist) can be avoided. However with the introduction of 1Gb-dynamic random access memory (DRAM) development, a paradigm shift is being experienced within the optical lithographic community. With 1Gb-DRAMs, the minimum feature size falls irreversibly below the optical wavelength used to image the feature. Such a situation will make low K1 factor imaging unavoidable. With 175 nm groundrules typical for first generation 1G-DRAMs, K1 factors near 0.4 will be common with 0.5 as an upper limit on advanced systems currently in development irrespective of optical wavelength. This paper will cover the selection process, experimental data, and problems encountered in defining and integrating the lithographic process used to support the critical mask levels on 1Gb-DRAM development. Factors considered include: resist, masks, and illuminations via both simulation and experiment. The simulations were conducted with both internal and externally developed software. The experimental data to be reviewed was generated using an experimental 0.6 NA KrF step and scan system provided by Nikon. The resist used is commercially available from the Shipley corporation.

The use of sendahead wafers to control a lithography sector severely limits the performance of that sector. As a result, the elimination of sendahead wafers is most desirable. Through the creation of a robust resist process, careful metrology and modeling of the jobs being processed, and through the use of statistical process control on key variables, we have achieved a Cp of .98 and a Cpk of .95 on an 800 nanometer linewidth, 200 nanometer overlay lithography technology. These results have been achieved on our 8 inch, GCA Autostep 200 2145 i-line steppers at the same time that sendahead wafers have been eliminated. This paper discusses the work done to stabilize the lithography sector and eliminate sendahead wafers, the introduction of statistical process control in that sector and the effects of that introduction on the quality of lots being processed. This paper also presents long term tool and process stability data.