The lithographic challenges of printing at low-k1 for 65 nm logic technologies have been well-documented (1,2). Heavy utilization of model-based optical proximity correction (OPC) and reticle enhancement technologies (RET) are the course of record for 65 nm logic nodes and below. Within the SRAM cells, often more dimensionally constrained than random logic, characterization of the nominal gate linewidth and linewidth variation is critical to ensure cell performance and stability. In this paper, we present the use of the linewidth roughness analysis package of a commercially-available CD SEM to extract low-spatial frequency information in order to characterize effects of OPC, substrate topography, process variations, and RETs. The SEM-based characterization of across-device linewidth variation is analyzed statistically to extract the information necessary to set device processing conditions and to make layout corrections consistent with producing the least possible channel length variation along the active device.

As lithographers continue to implement more exotic and complex resolution enhancement techniques (RET) to push patterning further beyond the physical limits of optical lithography, full-chip brightfield inspections are becoming increasingly valuable to help identify random and systematic defects that occur due to mask tolerance excursions, OPC inaccuracies, RET design errors, or unmanufacturable layout configurations. PWQ, or process window qualification, is a KLA-Tencor product using brightfield imaging inspection technology that has been developed to address the need for rapid full-chip process window verification. PWQ is currently implemented at IBM's 300 mm facility and is being used to isolate features that repeatedly fail as a function of exposure dose and focus errors. We will demonstrate how PWQ results have assisted in: 1) qualification of reticles and new OPC models; 2) identification of non-obvious lithographic features that limit common process windows; 3) providing input for long-term design for manufacturability (DfM), OPC, and/or RET modeling. PWQ allows full or partial chips to be scanned in far less time than a multi-point common process window collected on a SEM. PWQ findings supplement these traditional analysis methods by encompassing all features on a chip, providing more detail on where the process window truly lies. Examples of marginal features that were detected by PWQ methods and their subsequent actions will be discussed in this paper for an advanced 65 nm and a 90 nm CMOS process

The rapidly escalating complexity of resolution enhancement techniques (RET), now commonplace in leading edge lithography, requires accurate verification to avoid yield and performance problems on the patterned wafers. Model-based verification techniques that have been derived from optical proximity correction (OPC) obtain the required checking speed from sparse sampling of the layout at discrete evaluation points along the edges of layout patterns. This sparse sampling allows accurately calibrated models to be used for full chip checking applications. However, there is a demonstrated risk of missing significant patterning errors due to the sparse and edge-centric sampling of the layout. Grid-based simulation approaches which calculate the image on a fine grid over the entire layout space accurately detect patterning problems anywhere in the layout, but can be executed at reasonable runtimes for aerial image models only. The challenge for full-chip model-based verification of RET-enhanced layouts is, therefore, a trade-off between sparse, edge-centric simulation using accurate models versus simulations using approximate models over the entire layout space. This paper presents an approach, termed contourIFV, that has been demonstrated to overcome the aforementioned problems and has been shown to provide significant value in the verification of the RET and OPC prescription.

Optical Proximity Correction has emerged as an industry standard technique to reproduce the desired shapes on wafers as pattern dimensions are approaching the optical resolution limits. However secondary effects, if not properly controlled, may impede successful application of this technique. In order to better assess these factors we have divided the overall pattern formation process into several obvious components: The illumination system, mask, projection optics, resist system and finally etch processes. Each one of these components influences the optical proximity effects observed in the final pattern. The dependence of optical proximity corrections on the type of illumination is fairly well known and will only be touched on. Variations in the mask manufacturing process such as deviations of the mask critical dimension from its nominal value will be discussed. The type of e-beam exposure tool used to write the mask was found to have profound impact on optical proximity correction and therefore specifying the type of mask writing tool and sometimes even its writing mode to ensure reproducible results is required. Lens aberrations in the optical exposure tool and their impact were studied using aerial image simulations. Examples of optical proximity curves from different first generation tools show significant differences even between tools of the same type. Resist effects and the variations induced by modifying etch processes were investigated emphasizing that a fairly detailed control of the overall pattern formation process is necessary to successfully implement any OPC approach.

A general level-specific lithography optimization methodology is applied to the critical levels of a 1-Gb DRAM design at 175- and 150-nm ground rules. This three-step methodology-ruling out inapplicable approaches by physical principles, selecting promising techniques by simulation, and determining actual process window by experimentation-is based on process latitude quantification using the total window metric. The optimal lithography strategy is pattern specific, depending on the illumination configuration, pattern shape and size, mask technology, mask tone, and photoresist characteristics. These large numbers of lithography possibilities are efficiently evaluated by an accurate photoresist development bias model. Resolution enhancement techniques such as phase-shifting masks, annular illumination and optical proximity correction are essential in enlarging the inadequate process latitude of conventional lithography.

Many semiconductor chip designs require precise simultaneous control of both the width and length of asymmetric features. Line shortening due to optical, resist processing, and mask effects cause the process windows for width and length to diverge. Typically differential mask biasing has been used to maximize the common process window for both axes. As we enter the gigabit era limitations in grid size and mask write times may become significant restrictions to meeting required device tolerances with that approach.Simulations of aerial image and resist processing using SPLAT(1) and LEOPOLD2,3 indicate that for a given mask there is considerable latitude to adjust the length of features without a significant loss of process window. An experimental design matrix was used to verify the simulation results and develop a regression model of pupil fill, numerical aperture, and resist diffusion effects. This model was then applied to optimize the processing conditions for several product masks. This technique is particularly useful early in the development cycle when mask to mask repeatability is poor and lead times are long. It may also be used to fine tune image sizes in manufacturing.

The traditional lithographic approach employed by the semiconductor industry has been to pursue use of advanced prototype optical exposure tools and resists. The benefits of doing so have been: (1) The lithographic process that is used in development more closely resembles the process that will in fact be used to manufacture the chip. (2) The cost of low K1 imaging (phase-masks, off-axis illumination, and surface imaging resist) can be avoided. However with the introduction of 1Gb-dynamic random access memory (DRAM) development, a paradigm shift is being experienced within the optical lithographic community. With 1Gb-DRAMs, the minimum feature size falls irreversibly below the optical wavelength used to image the feature. Such a situation will make low K1 factor imaging unavoidable. With 175 nm groundrules typical for first generation 1G-DRAMs, K1 factors near 0.4 will be common with 0.5 as an upper limit on advanced systems currently in development irrespective of optical wavelength. This paper will cover the selection process, experimental data, and problems encountered in defining and integrating the lithographic process used to support the critical mask levels on 1Gb-DRAM development. Factors considered include: resist, masks, and illuminations via both simulation and experiment. The simulations were conducted with both internal and externally developed software. The experimental data to be reviewed was generated using an experimental 0.6 NA KrF step and scan system provided by Nikon. The resist used is commercially available from the Shipley corporation.

Introduction Phase-shifting masks (PSMs) [1][2] and modified illumination techniques [3] have shown promise in improving the resolution and process latitude of lithography. For 1 Gb-DRAM application, these techniques are essential because printing 175 nm features is pushing the limits of even high numerical aperture (NA) deep-UV exposure systems, and wavelength reduction is not an alternative until the availability of 193 nm exposure systems around the turn of the century. This paper explores the application of attenuated PSM [2] and alternating PSM [l], as well as annular illumination [3] in the optimization of lithographic performance at the 175 nm groundrule. Lithographic simulation including the effects of photoresist processing [4] was used to identify optimal conditions for critical levels of a 1 Gb-DRAM cell design [5], and improvement in performance was quantified experimentally. Process Optimization To ensure reliability of the 1 Gb cell requires the control of feature edge placement to within 17.5nm (&lo%). Based on this criterion, exposure-defocus analyses [6] were performed on the viable resolution enhancement techniques, and their relative merits are quantified in terms of depth-of-focus (DOF) with 10% exposure dose variation. Simulation is performed using SPLAT [7] and an internal IBM program LEOPOLD which models the important effects of photoresist processing. Fig. 1 shows the mask and illumination techniques examined. For each critical level, the three approaches which give the largest DOF (at 10% exposure latitude) are listed in Table 1 together with the design layout. The latitude obtained with conventional chromium (COG) mask and standard illumination is also included for reference. In general, annular illumination and alternating PSM are strong candidates for grating-like levels, while attenuated PSM provides the most benefit for contact levels. It is of interest to note the use of negative resist for the active area (AA) level. Fig. 2 illustrates the improvement in image integrity with resolution enhancement techniques for the AA level. The contours represent aerial image intensity in steps of 0.1 normalized to the clear field intensity. For a COG mask with standard illumination, the intensity contours are sparse in both the width (horizontal) and length (vertical) directions, indicating poor image quality and resulting in a DOF of only 0.4 pm. For an attenuated PSM with annular illumination, the intensity contours are denser, resulting in an improved DOF of 1.2 pm. With an alternating PSM at a reduced partial coherence factor of 0.3, the intensity gradient is especially steep at the ends of the feature due to the effects of phase-shifting. This manifests as a better DOF of 1.4 pm and improved line-end shortening behavior: the length is only biased at lOOnm as opposed to 150nm on the COG and attenuated PSM. Mask imperfection limits and in some cases obliterates the benefits of PSMs. Fig. 3 shows the DOF for a 225nm bitline contact (CB) with different types of mask imperfection. With an ideal attenuated PSM, the best DOF exceeds 2.0 pm. This DOF decreases to 1.4 pm with f5 nm of mask critical dimension (CD) error. With the addition of 410.5% transmission and f 5 " phase variation, the DOF is further degraded to 0.4 pm, virtually indistinguishable from that of a COG mask with f 5 nm of mask CD error. Thus, transmission and phase control of the attenuated PSM must be better than f0.5% and ~ t 5 ' respectively for it to have any advantage over COG masks on the CB level. Experimental Results Biased COG and PSM reticles were fabricated for the deep trench (DT), AA, gate conductor (GC), bitline (MO), and CB levels. The reticles were exposed on a Nikon deep-UV step-andscan system (A = 248nm, N A = 0.6, CT = 0.6). For annular illumination, the inner and outer radii correspond respectively to U = 0.5 and (r = 0.75. The positive [8] and negative [9] resists are 0.6 pm and 0.5 pm thick, respectively. Table 2 summarizes the DOF (at 10% EL) for various levels determined from top-down scanning electron micrograph (SEM) measurement. The use of resolution enhancement techniques improve the process latitude of all levels. Of particular interest is the AA level, which calls for the use of negative photoresist. Fig. 4 shows the top-down SEMs of AA patterns exposed with annular illumination and attenuated PSM in negative resist over a 1 .O pm focus range. The DOF is approximately 0.8 pm between the focus at which the pattern loses integrity (-1.2 pm) and the focus at which stringers are observed (-0.2 pm). In a DRAM chip, it is important to print both the array and peripheral patterns. In some cases, the use of resolution enhancement techniques improves the process latitude of array features but degrades the integrity of peripheral patterns. For example, while the use of annular illumination in the MO level improves the grating-like array patterns, the end line of the peripheral feature shows signs of necking and bridging as shown by the SEM in Fig. 5. This problem can be remedied by biasing of the outer line and modifying the etch process. Conclusion Level-specific lithography optimization for a 1 Gb DRAM cell has been demonstrated based on simulation and experimental studies. Results indicate that the optimal lithographic approach is strongly dependent on feature pattern. The use of resolution enhancement techniques for process improvement within the array may lead to modifications of design rule for peripheral features. PSM imperfection due to fabrication may also limit the benefits of such masks. References [I] M. Leuenson, N Viawanatha", and R Simpson, "Improving Resolution ~n Photolithography with a Phase-shifting Mask." IEEE Trans. Electron Devices, voI ED-29, no. 12, pp. 1812-1846, December 1982 (21 B Lin. "The Attenuated Phase-shifting Maek," Solid State Tech., voi 35, no. 1 . pp. 43-47. January 1992 [3] K Kamon. T. Miyamoto, Y. Myoi, H Tanaka, and M Tanaka. "Photolithography System Using Modified Illumination," Jpn. J . Appl. Phys , YOI 32. no 1 A . pp. 239243, 1993 [4] T . Brunner and R . Ferguson, "Simple m o d e l s for resist processing effects," Solid State Tech., p p . 95-103. June 1996. 151 the 1Gb cell 1 s an extension of the cell in L . Nesbrt, et a i . , " 0 . 6 w m 2 5 6 M b trench DRAM cell with self-aligned BuriEd STrap (BEST) ," IEDM Technical Digest, pp 627630, 1993. [6] B Lin, "Partially Coherent Im=ging ~n Two-dimensions and Theoretical Llmits of Projection Printing in Microfabrication." IEEE Trans. Electron Devices. vol. ED-27, p. 931 , 1980 [7] K . Toh, "Two-dimensional Images with Effects of Lens Aberrations jn Optical Lithography." M. S. Thesis, Memorandum No UCB/ERL M88/30, University of Callfornia, Berkeley, May 1988 [SI W . Conley, e t al. "The Lithographic Performance of an Environmentally Stable Chemically Amplified Photoresist (ESCAP) ," Proc SPIE, "01 2724, pp 34-60. 1996. 191 W. Conley, et al , "Negative DUV Photoresist for 1 6 M b DRAM Production and Future Generations," Proc SPIE, YOI 1925. pp 120-132, 1993

At low k1 factors, optical proximity correction (OPC) is used to correct line size such that what is delivered by the lithography process is closer to the design dimension than an uncorrected process would deliver. OPC is usually derived for perfect masks and exposures. Random variation of the mask critical dimension (CD), wafer exposure latitude, and wafer defocus are examined for their effects on an OPC mask. Expected CD variation in the aerial image is given for each of these variables. Examining these variables will also give insight as to how fine an OPC can realistically be obtained, and how fine a grid size is needed in the manufacture of the mask.

An approach for design-specific lithography optimization using simulation and experimental validation has been demonstrated for a 256 Mb DRAM cell. Results from this study indicate that the optimum lithographic solution has a strong dependence on pattern shape and density. Initial emphasis in the implementation of resolution-enhancement techniques should be placed on the development of attenuated phase-shifting masks as well as off-axis illumination. These efforts must continue to strive towards extending lithographic performance beyond current capabilities at 0.25 /spl mu/m groundrules.<>