Graphene is a promising ultra-thin barrier against undesired mass transport, however, the high deposition temperatures or the defect inducing post-deposition transfer processes limit its widespread applicability. Herein we report on the successful blocking of copper (Cu) ion diffusion by large area multi-layer graphene (MLG) membranes deposited directly on silicon oxide (SiO2) via low temperature plasma-enhanced chemical vapor deposition. The barrier strength of MLG is compared to evaporated tantalum (Ta) by applying positive bias-temperature stress (BTS) to Cu/barrier/SiO2/Si test structures. After constant BTS of 4 × 106 V cm-1 at 400 K for 50 min, the MLG barrier device exhibits a negligible flat band voltage shift in capacitance-voltage measurements and no discernible current peak in triangular voltage scans, whereas the Ta barrier allows significant Cu ion transport. Highly limited Cu ion diffusion through MLG suggests that lower energy diffusion paths, like grain boundaries and defects of individual graphene layers, do not align in the direction of an applied stress field. In general, the presented low-temperature direct growth MLG membranes can block undesirable diffusion in many applications, and are especially suitable as Cu diffusion barriers in integrated circuit chips, photovoltaic cells and flexible electronic devices.

Sub-1 nm Cu difïusion barriers are realized by using transferred CVD-grown hexagonal boron nitride (h-BN) and directly deposited molybdenum disulfide (MoS 2 ), for the first time. Based on time-dependent dielectric breakdown measurements, the diffusion barrier properties of these 2D materials are explored to address the barrier/liner scaling challenge for the ultra-scaled interconnect technology. The predicted lifetime of devices with directly deposited 2D barriers can achieve 3 orders of magnitude improvement compared to control devices.

Due to the small skin depth in metals at optical frequencies, their plasmonic response is strongly dictated by their surface properties. Copper (Cu) is one of the standard materials of choice for plasmonic applications, because of its high conductivity and CMOS compatibility. However, being a chemically active material, it gets easily oxidized when left in ambient environment, causing an inevitable degradation in its plasmonic resonance. Here, for the first time, we report a strong enhancement in the optical relaxation time in Cu by direct growth of few-layer graphene that is shown to act as an excellent passivation layer protecting Cu surface from any deterioration. Spectroscopic ellipsometry measurements reveal a 40–50% reduction in the total scattering rate in Cu itself, which is attributed to an improvement in its surface properties. We also study the impact of graphene quality and show that high quality graphene leads to an even larger improvement in electron scattering rate. These findings are expected to provide a big push towards graphene-protected Cu plasmonics.

Highly conductive copper nanowires (CuNWs) are essential for efficient data transfer and heat conduction in wide ranging applications like high-performance semiconductor chips and transparent conductors. However, size scaling of CuNWs causes severe reduction in electrical and thermal conductivity due to substantial inelastic surface scattering of electrons. Here we report a novel scalable technique for low-temperature deposition of graphene around CuNWs and observe strong enhancement of electrical and thermal conductivity for graphene-encapsulated CuNWs compared to uncoated CuNWs. Fitting the experimental data with the theoretical model for conductivity of CuNWs reveals significant reduction in surface scattering of electrons at the oxide-free CuNW surfaces, translating into 15% faster data transfer and 27% lower peak temperature compared to the same CuNW without the graphene coating. Our results provide compelling evidence for improved speed and thermal management by adapting the Cu-graphene hybrid technology in future ultrascaled silicon chips and air-stable flexible electronic applications.

Conventional Chemical Vapor Deposition (CVD) techniques require the use of a catalyst surface and high temperature of growth (∼1000°C) to grow graphene, which renders the process incompatible with arbitrary substrates. While post-synthesis transfer of graphene onto required substrates is widely used, it causes undesirable effects such as wrinkles/folds/cracks and unintentional doping. Here, we report low-temperature growth of graphene at 650°C on non-catalytic SiO2 and quartz substrates using a one-step, rapid Plasma Enhanced Chemical Vapor Deposition (PECVD) process. We simultaneously study PECVD graphene growth on a traditional catalytic material such as copper and show that the growth substrate does not play any role in the dissociation of hydrocarbon precursor during PECVD, thus eliminating the possibility of a catalytic effect. Using several characterization techniques, we observe an increasing rate of growth from SiO2 to quartz to copper, which can be attributed to different adsorption and diffusion energies of plasma radicals on these substrates. As opposed to thermal CVD growth on copper, which is self-limiting, the PECVD method developed here is scalable in terms of number of layers, allowing its adept integration in commercial devices.

In this article, we experimentally demonstrate for the first time high performance ionic liquid gated Schottky barrier WSe 2 FETs with large current drive capabilities for both the electron and the hole branch. We also show that through proper scaling of the flake thickness, the Schottky barrier can be made transparent to the carrier injection and thus transforming the metal contacts into pseudo-Ohmic ones. We also analyzed the tunneling current through the Schottky barrier and compared it with numerical simulations in order to evaluate the potential of WSe 2 for low power applications. WSe 2 belongs to the family of two-dimensional layered semiconducting transition metal dichalcogenides (TMDs) which have received substantial attention in the device community as alternative channel materials to Si. [1] WSe 2 is especially interesting since it shows ambipolar conduction due to the pinning of metal Fermi level close to the middle of the bandgap. [2] In addition, the relatively small carrier effective mass [3] of WSe 2 in comparison to other TMDs makes this material appealing for low power tunneling devices.

In this paper, the impact of process/technology co-optimization on System-on-Chip (SoC) performance using detailed 3-D process/device simulations has been studied for nanoscale FinFET devices. We investigated challenges in FinFET device optimization and scaling while using standard ion implantation process for both overlap and underlap designs. Moreover, an implant-free (IF) complementary metal-oxide-semiconductor process is discussed for better scalability with improved performance. FinFETs designed using this IF process shows a similar to 2x improvement in static random-access memory and digital input/output performance. Additionally, a modification to the IF process is proposed, which further helps in achieving an improved logic and analog performance for overall SoC development.