A - (480 m)-pixel cardiac ultrasound patch LTPS TFT system on flexible substrate is presented in this paper. The design is capable of selecting emission windows on both horizontal and vertical direction enabling 2D beamsteering at 5 kfps. The system is verified for 10Vpp 500 kHz transducer signal with an SNR of 39.82 dB. Power dissipation is measured 7.72 mW. Non-uniformity of the signal inside the emission is measured below 0.3%. High-voltage gate drivers enable 60 Vpp output from 3.3-V input. A short transistor suppresses cross-talk by more than 3.

Positive Bias Temperature Instability (PBTI) degradation is studied at stress voltages of 25-45 V and at room and elevated temperatures in low-temperature polysilicon (LTPS) Thin Film Transistors (TFTs). Positive threshold voltage shifts observed in both n-and p-TFTs cannot be explained by the typically-reported amphoteric Si dangling bonds. Two apparently-independent and counteracting PBTI degradation mechanisms (components) are identified in similarly-degrading n-and p-TFTs. The generation component is seen to be driven by gate bias and at most weakly dependent on temperature T, unlike the strongly T-dependent counteracting "anomalous" annihilation component. The time kinetics of both components are proposed.

ABSTRACT A ‐ (480 m)‐pixel cardiac ultrasound patch LTPS TFT system on flexible substrate is presented in this paper. The design is capable of selecting emission windows on both horizontal and vertical direction enabling 2D beamsteering at 5 kfps. The system is verified for 10V pp 500 kHz transducer signal with an SNR of 39.82 dB. Power dissipation is measured 7.72 mW. Non‐uniformity of the signal inside the emission is measured below 0.3%. High‐voltage gate drivers enable 60 V pp output from 3.3‐V input. A short transistor suppresses cross‐talk by more than 3 .

Temperature plays a crucial role in influencing the quality of a package, especially in the cold supply chain. By using intelligent packaging to detect the exposure to heat, the status of these products can be retrieved. Critical Temperature Indicator (CTI) and Radio Frequency Identification (RFID) technology are integrated to monitor and communicate the package status by combined visual and electronic detection. Hereby, this work presents the development of an intelligent label integrating a polyaniline (PANI)-based sensor and a RFID antenna, both fabricated using Aerosol Jet Printing (AJP). The label is specifically made of a CTI which changes color upon an external trigger, and an RFID antenna that allows verifying the status of the device electronically; both components are printed on a paper label toward the development of an "intelligent label". The future applications use temperature as the triggering mechanism. The work primarily focuses on the design, fabrication, and testing of this device as a proof-of-concept. Particularly, the recipe of the own-developed PANI, the establishment of best printing strategies, and the identification of the intelligent label performance are described. By emphasizing manufacturing strategies, this work provides a foundation for scalable, printed devices tailored for smart monitoring applications.

This paper contains an analysis of an ultrasound pulse-echo system with a TFT backplane, and considers how the trade-off between resistance, capacitance and voltage tolerance can be navigated during technology development To this end, the link budget is calculated, the losses in the backplane are quantified, the optimal device width is calculated and a contour plot with the trade-off between the performance and voltage tolerance is shown

Targeting large-area analog sensing applications, a compact modeling framework is proposed for lowtemperature polycrystalline silicon (LTPS) thin-film transistors (TFTs). The model captures both static and statistical characteristics. Five key parameters ($K, V_{\text {th }}, S S, \theta, \lambda$) are extracted per device by fitting measured $I_{D S}-V_{D S}$ curves. Statistical analysis is conducted from both technology-corner and mismatch perspectives. Devices are clustered into fast, typical, and slow technology corners; combined corners are then formed by pairing N-type and P-type classifications, and their distribution across 15 cm substrate is analyzed. Mismatch is characterized by analyzing the spatial correlation of TFTs, from which local and global variation coefficients are derived. Circuit-level validation is performed using a folded-cascode operational transconductance amplifier (OTA) and a dynamic comparator, both fabricated in the same LTPS process. Measurements from 45 OTAs and 7 comparators confirm the accuracy and robustness of the model.

The use of fiber-based papers as substrates for the smart packaging industry holds great promise for future green and sustainable electronics. However, this area has not been extensively explored so far, and the manufacturing of paper-based electronics is still at its early stages. In this work, 16 different paper-based substrates were characterized based on their properties, including surface roughness, ink–substrate response, and ability to withstand thermal sintering. The best paper-based substrate was further selected for Aerosol Jet® Printing (AJ®P) using a silver nanoparticle ink. The electrical performance of the printed lines was evaluated to assess the AJ printability of the investigated substrates, while their reliability and durability were further characterized through accelerated aging tests (including climate and light exposure) and resistance to water and rubbing. Finally, a high-frequency radio frequency identification antenna tag was AJ printed as a case study of a smart and flexible electronics for packaging, and its frequency response was successfully validated. This study demonstrates the use of AJP on sustainable fiber-based substrates as an effective printing technique to serve the needs of a sustainable, smart packaging industry.

We demonstrate an electro-structural integration approach to define piezoelectric micromachined ultrasound transducers (PMUT) on top of thin-film-transistor (TFT) backplanes for imaging applications, enabling large-area, low-cost transducer arrays. While the piezo stacks for these microelectromechanical structures (MEMS) are manufactured in a silicon foundry, the switches for element addressing are made separately using a standard TFT process, in a flat-panel-display fab. Cu/Ni/Sn microrings are processed on top of the piezo stack at wafer level, before a flip-chip assembly approach bonds a single thinned silicon die to the Ni/Au stack atop the TFT-on-glass die. The assembled devices are tested mechanically, electrically, and acoustically. A pulse-echo based 2D imaging demonstration is presented.

This paper presents a proof-of-concept for manufacturing ultrasound transducers on top of a TFT switch matrix. The novel process incorporates a bonding step crucial for both mechanical and electrical connections between the PMUT frontplane and the TFT backplane. Considering this specific boundary condition, the PMUT device is designed to emit a maximum pressure generated by the PMUT membrane itself minimizing the effect of the crosstalk inter PMUT. Initial measurements are compared to simulation results, demonstrating good alignment. Additionally, the paper showcases an image generated by a PMUT array operating at 3MHz.

We present a thin‐film piezoelectric micromachined ultrasonic transducer (PMUT) technology compatible with flat‐panel manufacturing methods. Using the developed flow which is based on a low temperature AlScN piezoelectric layer, we fabricate large area 48x48 element PMUT arrays on glass. Beam steering and ultrasound medical imaging are demonstrated. The developed transducer technology can be combined with a TFT backplane and has the potential of direct integration on top of display size glass sheets, expanding the boundaries of ultrasound application domains.

Printed Electronics (PE) involves additive deposition of functional materials on a substrate via printing processes to realize electronic circuits, interconnects, electrical components or devices. This methodology is opposite to the conventional microelectronics industry which is based on subtractive manufacturing techniques (e.g. etching). Some of the advantages of PE over conventional electronics are low prototyping costs, short time to market, less processing steps, etc. One of the features is the ability to manufacture flexible and customized products and devices. The applications of Printed Electronics apply to different sectors of industry like electronics, packaging, bio-medical, automotive, communication, etc. In this work, we present Aerosol Jet® Printing (AJ®P) and Screen Printing as two techniques for the realization of flexible and mass customized PE devices. Whereas the use of AJ®P is focused on rapid prototyping, Screen Printing allows to upscale for mass production. The two technologies are here implemented to realise conductive antennas on paper substrates, potentially to integrate into a delivery parcel box for the development of "smart packaging". This antenna design is based on the 13.56 MHz working frequency, which lies in the frequency spectrum of HF RFID/NFC applications. The print quality, electrical resistance and the basic functional characterization (working frequency) of these paper-based antennas are here investigated and reported.

Intelligent packaging is an emerging technology, aiming to improve the standard communication function of packaging. Radio frequency identification (RFID) assisted smart packaging is of high interest, but the uptake is limited as the market needs cost-efficient and sustainable applications. The integration of screen printed antennas and RFID chips as smart labels in reusable cardboard packaging could offer a solution. Although paper is an interesting and recyclable material, printing on this substrate is challenging as the ink conductivity is highly influenced by the paper properties. In this study, the best paper/functional silver ink combinations were first selected out of 76 paper substrates based on the paper surface roughness, air permeance, sheet resistance and SEM characterization. Next, a flexible high frequency RFID chip (13.56 MHz) was connected on top of screen printed antennas with a conductive adhesive. Functional RFID labels were integrated in cardboard packaging and its potential application as reusable smart box for third party logistics was tested. In parallel, a web-based software application mimicking its functional abilities in the logistic cycle was developed. This multidisciplinary approach to developing an easy-scalable screen printed antenna and RFID-assisted smart packaging application is a good example for future implementation of hybrid electronics in sustainable smart packaging.

RFID tags are embedded in everyday objects providing extra functionalities and aiming to connect them to the cloud. Miniaturization of flexible RFID tags enables the integration into smaller everyday health, entertainment, food related objects, besides enhancing security and decreasing the cost. In addition, external sensor integration and readout enable new applications for the sensor tags. In this paper a miniaturized 2cm (1€ coin size) diameter antenna is combined with a flexible InGaZnO thin-film RFID chip operating at 3V and transmitting data at 7.3kHz. Moreover, the sharp threshold detection (<500k Ω) of a resistive temperature sensor is demonstrated using the same technology, enabling multi-threshold detection on flexible and ultrathin (<15µm) substrates.

The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated three-dimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology.In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, III-V, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000.In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay.The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.

Spin-transfer torque magnetoresistance random access memory is a major contender for static random access memory replacement in embedded caches at advanced fin field effect transistor nodes. It suffers, however, from the low resistance difference between the bistable states of the magnetic tunnel junction (MTJ). Variability on MTJ resistance and access transistors makes reliable read-out even more challenging. This triggered the use of complementary cells for low level caches needing high performance. This paper, focusing on the lower level caches, shows an improved 3T 2MTJ cell with a ground grid and a novel three transistor read and write operation to improve area density, sense margin, write performance, and write energy consumption. Despite the cell's three transistors, the improved array configuration reduces the cell area by 22% as compared with the 2T 2MTJ cell, making it only 55% larger than a 1T 1MTJ cell. The novel mismatch tolerant read operation uses all three transistors and increases the sense margin by up to 88%. The novel variation resilient write operation also uses all three transistors and takes advantage of the inherent MTJ characteristics and complementary operation of the cell. This increases the write performance by 2x and reduces the write energy by 3x compared with the 2T 2MTJ cell and by 1.5x compared with the 1T 1MTJ cell.

Static Random Access Memory (SRAM) cells are used together with logic standard cells as the benchmark to develop the process flow for new logic technologies. In order to achieve successful integration of Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) as area efficient higher level embedded cache, it also needs to be included as a benchmark. The simple cell structure of STT-MRAM brings extra patterning challenges to achieve high density. The two memory types are compared in terms of minimum area and critical design rules in both the iN10 and iN7 node, with an extra focus on patterning options in iN7. Both the use of Self-Aligned Quadruple Patterning (SAQP) mandrel and spacer engineering, as well as multi-level via’s are explored. These patterning options result in large area gains for the STT-MRAM cell and moreover determine which cell variant is the smallest.

The series resistance of STT-MRAM cells becomes increasingly important in deeply scaled nodes. Next to the typical scaling of width and thickness of the copper layers, barriers further reduce the cross-section of the actual copper. Moreover, at these small sizes, the resistivity of copper degrades compared to bulk copper. This paper presents a novel STT-MRAM cell design with partial source line planes, which improves the trade-off between area and source line resistance. A single source line is shared among multiple bit line rows of the embedded memory array, resulting in a smaller cell area at the same source line resistance or a reduced resistance at the same area. The design with a partial source line plane shared among 4 bit line rows results in an area reduction of 11% at the same source line resistance. Alternatively, at the same area, the source line resistance is reduced by more than a factor of 4. The reduced series resistance of the cell results in a performance gain and a reduction of energy consumption.

Lattice Reduction aided soft output MIMO detectors (LR-SOMD) have been demonstrated to offer a promising gain. This work explores the potential of implementing a LR-SOMD on a parallel programmable baseband processor. In this paper, first a LR algorithm called the Data Regularized Parallel Lattice Reduction algorithm (DRP-LR) is proposed. Afterwards, a low-complexity LR-SOMD, Radius Constrained Multi-Tree Selective Spanning (RC-MTSS) is presented. RC-MTSS uses a novel multiple-tree search approach for LR-SOMD, while combining the benefits of Sphere Detection (SD) and Selective Spanning with Fast Enumeration (SSFE). A fixed complexity LR-SOMD, Multi-Tree Selective Spanning (MTSS) is also proposed for implementation. Both the algorithms, DRP-LR and MTSS, are enabled to exploit data level parallelism (DLP) and instruction level parallelism (ILP). In order to evaluate performance, the proposed DRP-LR and MTSS are implemented on the ADRES baseband processor for a 4 × 4 LTE system using QAM-64. DRP-LR achieves an average throughput of 33.33 M LR per second, which is comparable to recently reported ASIC implementations, while MTSS shows an average throughput of 730 Mbps on the same processor. To the best of authors' knowledge, this is the first reported implementation of a LR-SOMD algorithm on a parallel programmable baseband processor.

Emerging high throughput wireless communication standards, such as LTE/LTE-A and IEEE 802.11ac, impose exciting challenges on SDR baseband implementations. Our work explores the feasibility of SDR baseband for the most demanding-modes in those emerging high throughput standards. On a customized C programmable SDR baseband processor (with compiler support), we have accomplished realtime inner receiver implementations for Cat-4/5/7 LTE/LTE-A UE and up to the 80MHz 4 × 4 mode of IEEE 802.11ac. The implemented inner receiver includes all essential synchronization and data detection functionalities, including coarse CFO estimation/compensation, I/Q imbalance estimation/compensation, OFDM(A) demodulation, channel estimation, fine SCO/CFO estimation/compensation, channel tracking, MIMO channel processing, MIMO data detection, LLR generation, etc..

The Chinese Digital Television Terrestrial Broadcasting System has a complex PHY layer definition with many different modes including two different block transmission schemes (OFDM and SC) and three different known symbol padding cyclic extensions, some of which with phase rotation between blocks that break the cyclicity. The block sizes with or without cyclic extension are “non power of two” numbers. This plurality of modes and the unusual block sizes make the design of a signal processing architecture very difficult. In addition, the known symbol padding extensions are intended for channel estimation but have poor auto-correlation properties; hence the channel estimation in long multipath channels is degraded and not suitable for high order constellations. We have designed a novel unified receiver architecture supporting all modes of this broadcasting system, capable to start from a poor initial channel estimation. We describe in detail this architecture and provide simulation results supporting our system choices.