Constrained random verification in industrial settings involves parameterized tests. The parameters used to control the test stimuli generation are typically set when the test is first written, and seldomly varied later on in nightly regressions. In this work, we formulate test parameter configuration as a blackbox optimization problem and introduce Smart Regression Planner (SRP), an approach that automatically configures the tunable test parameters to better explore the input space and accelerate convergence towards coverage. The optimizer in SRP can drive the parameters update with a Bayesian optimization technique that uses coverage from nightly regressions as feedback. Our evaluation on open-source as well as larger industrial designs demonstrates that SRP leads to up to 9.84% higher average coverage over 100 nights than the human baseline. Importantly, it converges to coverage milestones up to 20 × faster than the human baseline. With high-level test parameter optimization, we introduce a problem space and an opportunity to achieve categorically higher coverage in industrial settings with very low overhead. Furthermore, through two practical use cases, we show that employing multi-objective optimization and transfer learning can further accelerate the verification process. to structure and flexible enough to adapt to changes in an evolving design. While random search relies purely on exploration, Bayesian optimization exploits learning through feedback. We also investigate use cases of (1) simultaneously minimizing runtime and maximizing coverage using multi-objective Bayesian optimization, and (2) transfer learning, or the ability to transfer learned heuristics from one set of parameters to another through design evolution. practical impact, at an abstraction level where scalability is a natural byproduct. We have shown that employing Bayesian optimization to adjust parameters in a testbench allows us to improve coverage in real industrial settings. The improvement comes at a very low engineering overhead: the system can be assembled from standard commercial RTL simulators and off-the-shelf blackbox optimizers, and involves no effort from the verification engineers once set up. Furthermore, we show that through multi-objective optimization, it is possible to improve both test run-time and coverage (leading to more efficient use of simulator licenses and compute), and through transfer learning, it can effectively handle continuously evolving designs and testbenches (as is a requirement in practice).

Verification is a serious bottleneck in the industrial hardware design cycle, routinely requiring person-years of effort. Practical verification relies on a "best effort" process that simulates the design on test inputs. This suggests a new research question: Can this simulation data be exploited to learn a continuous representation of a hardware design that allows us to predict its functionality? As a first approach to this new problem, we introduce Design2Vec, a deep architecture that learns semantic abstractions of hardware designs. The key idea is to work at a higher level of abstraction than the gate or the bit level, namely the Register Transfer Level (RTL), which is somewhat analogous to software source code, and can be represented by a graph that incorporates control and data flow. This allows us to learn representations of RTL syntax and semantics using a graph neural network. We apply these representations to several tasks within verification, including predicting what cover points of the design will be exercised by a test, and generating new tests that will exercise desired cover points. We evaluate Design2Vec on three real-world hardware designs, including an industrial chip used in commercial data centers. Our results demonstrate that Design2Vec dramatically outperforms baseline approaches that do not incorporate the RTL semantics, scales to industrial designs, and can generate tests that exercise design points that are currently hard to cover with manually written tests by design verification experts.

Constrained random verification (CRV) in industrial settings involves manual parameterized test generation, a costly and inefficient process. We formulate test parameter configuration as a blackbox optimization problem and we introduce Smart Regression Planner (SRP), an approach that automatically configures the tunable test parameters to better explore the input space and accelerate convergence towards coverage. The optimizer in SRP can drive the parameters update with twomethods: a light-weight random search, and a Bayesian optimization technique that uses coverage from nightly regressions as feedback. Our experimental evaluation on open-source as well as larger industrial designs demonstrates that frequent perturbation and optimization of test parameters leads to higher coverage than the human baseline. Importantly, it converges to coverage milestones significantly faster than the human baseline. With high-level test parameter optimization, we introduce a problem space and an opportunity to achieve categorically higher coverage in industrial settings with very low overhead.

Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research 1 , chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area. To achieve this, we pose chip floorplanning as a reinforcement learning problem, and develop an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip. As a result, our method utilizes past experience to become better and faster at solving new instances of the problem, allowing chip design to be performed by artificial agents with more experience than any human designer. Our method was used to design the next generation of Google’s artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation. Finally, we believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields.

Video sharing (e.g., YouTube, Vimeo, Facebook, TikTok) accounts for the majority of internet traffic, and video processing is also foundational to several other key workloads (video conferencing, virtual/augmented reality, cloud gaming, video in Internet-of-Things devices, etc.). The importance of these workloads motivates larger video processing infrastructures and – with the slowing of Moore’s law – specialized hardware accelerators to deliver more computing at higher efficiencies. This paper describes the design and deployment, at scale, of a new accelerator targeted at warehouse-scale video transcoding. We present our hardware design including a new accelerator building block – the video coding unit (VCU) – and discuss key design trade-offs for balanced systems at data center scale and co-designing accelerators with large-scale distributed software systems. We evaluate these accelerators “in the wild" serving live data center jobs, demonstrating 20-33x improved efficiency over our prior well-tuned non-accelerated baseline. Our design also enables effective adaptation to changing bottlenecks and improved failure management, and new workload capabilities not otherwise possible with prior systems. To the best of our knowledge, this is the first work to discuss video acceleration at scale in large warehouse-scale environments.

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU) --- deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X -- 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X -- 80X higher. Moreover, using the CPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

This article consists of a collection of slides from the author's conference presentation on the special features, supercomputing capabilities; system design and architectures, processing capabilities, and targeted markets for D.E. Shaw Research's ANTON2 chip, a massively parallel supercomputer.

Anton 2 is a second-generation special-purpose supercomputer for molecular dynamics simulations that achieves significant gains in performance, programmability, and capacity compared to its predecessor, Anton 1. The architecture of Anton 2 is tailored for fine-grained event-driven operation, which improves performance by increasing the overlap of computation with communication, and also allows a wider range of algorithms to run efficiently, enabling many new software-based optimizations. A 512-node Anton 2 machine, currently in operation, is up to ten times faster than Anton 1 with the same number of nodes, greatly expanding the reach of all-atom bio molecular simulations. Anton 2 is the first platform to achieve simulation rates of multiple microseconds of physical time per day for systems with millions of atoms. Demonstrating strong scaling, the machine simulates a standard 23,558-atom benchmark system at a rate of 85 μs/day -- 180 times faster than any commodity hardware platform or general-purpose supercomputer.

Applying formal methods to assist in the post-silicon debugging of complex digital designs presents challenges that are distinct from those found in pre-silicon formal verification. In post-silicon debug, a set of observed events or conditions describes a failure scenario. The task is to identify a reasonably general set of input and hardware state conditions that inevitably produces that failure scenario. That set of conditions may be represented in the form of a counterexample to a desired property. Modern formal verification methods are especially adept at finding counterexamples to properties, and can often do so efficiently in large state spaces. This paper describes a method of assisting the discovery of counterexamples using userhypothesized preconditions, or waypoints, of the failure. Each waypoint is an event that is believed to occur prior to the observed failure of the target property. By guiding formal analysis through a sequence of waypoints, the time required to find a counterexample of the target property can be significantly reduced. A specific case study is presented to illustrate the application and performance of our method using an actual example from the post-silicon debug of a 33-million–gate chip.

One of the major design verification challenges in the development of Anton, a massively parallel special-purpose machine for molecular dynamics, was to provide evidence that computations spanning more than a quadrillion clock cycles will produce valid scientific results. Our verification methodology addressed this problem by using a hierarchy of RTL, architectural, and numerical simulations. Block- and chip-level RTL models were verified by means of extensive co-simulation with a detailed C++ architectural simulator, ensuring that the RTL models could perform the same molecular dynamics computations as the architectural simulator. The output of the architectural simulator was compared to a parallelized numerical simulator that produces bitwise identical results to Anton, and is fast enough to verify the long-term numerical stability of computations on Anton. These explicit couplings between adjacent levels of the simulation hierarchy created a continuous verification chain from molecular dynamics to individual logic gates.

Design verification of complex digital circuits typically starts only after the register-transfer level (RTL) description is complete. This frequently makes verification more difficult than necessary because logic that is intrinsically hard to verify, such as memories, counters and deep first-in, first-out (FIFO) structures, becomes immutable in the design. This paper proposes a new approach that exploits formal verification of conditional coverage points with the goal of early identification of hard-to-verify logic. We use the difficulty of formal verification problems as an early estimator of the verification complexity of a design. While traditional verification methods consider conditional coverage only in the design verification phase, we describe an approach that uses conditional coverage at a much earlier stage-the design phase, during which changes to the RTL code are still possible. The method is illustrated using real examples from the verification of an ASIC designed for a specialized supercomputer.

The ability to perform long, accurate molecular dynamics (MD) simulations involving proteins and other biological macro-molecules could in principle provide answers to some of the most important currently outstanding questions in the fields of biology, chemistry and medicine. A wide range of biologically interesting phenomena, however, occur over time scales on the order of a millisecond--about three orders of magnitude beyond the duration of the longest current MD simulations. In this paper, we describe a massively parallel machine called Anton, which should be capable of executing millisecond-scale classical MD simulations of such biomolecular systems. The machine, which is scheduled for completion by the end of 2008, is based on 512 identical MD-specific ASICs that interact in a tightly coupled manner using a specialized high-speed communication network. Anton has been designed to use both novel parallel algorithms and special-purpose logic to dramatically accelerate those calculations that dominate the time required for a typical MD simulation. The remainder of the simulation algorithm is executed by a programmable portion of each chip that achieves a substantial degree of parallelism while preserving the flexibility necessary to accommodate anticipated advances in physical models and simulation methods.

OBJECTIVE—We determined whether muscle AMP-activated protein kinase (AMPK) has a role in the development of insulin resistance. RESEARCH DESIGN AND METHODS—Muscle-specific transgenic mice expressing an inactive form of the AMPK α2 catalytic subunit (α2i TG) and their wild-type littermates were fed either a high-fat (60% kcal fat) or a control (10% kcal fat) diet for 30 weeks. RESULTS—Compared with wild-type mice, glucose tolerance in α2i TG mice was slightly impaired on the control diet and significantly impaired on the high-fat diet. To determine whether the whole-body glucose intolerance was associated with impaired insulin sensitivity in skeletal muscle, glucose transport in response to submaximal insulin (450 μU/ml) was measured in isolated soleus muscles. On the control diet, insulin-stimulated glucose transport was reduced by ∼50% in α2i TG mice compared with wild-type mice. High-fat feeding partially decreased insulin-stimulated glucose transport in wild-type mice, while high-fat feeding resulted in a full blunting of insulin-stimulated glucose transport in the α2i TG mice. High-fat feeding in α2i TG mice was accompanied by decreased expression of insulin signaling proteins in gastrocnemius muscle. CONCLUSIONS—The lack of skeletal muscle AMPK α2 activity exacerbates the development of glucose intolerance and insulin resistance caused by high-fat feeding and supports the thesis that AMPK α2 is an important target for the prevention/amelioration of skeletal muscle insulin resistance through lifestyle (exercise) and pharmacologic (e.g., metformin) treatments.

AMP-activated protein kinase (AMPK) is widely recognized as an important regulator of glucose transport in skeletal muscle. The p38 mitogen-activated protein kinase (MAPK) has been proposed to be a component of AMPK-mediated signaling. Here we used several different models of altered AMPK activity to determine whether p38 MAPK is a downstream intermediate of AMPK-mediated signaling in skeletal muscle. First, L6 myoblasts and myotubes were treated with AICAR, an AMPK stimulator. AMPK phosphorylation was significantly increased, but there was no change in p38 MAPK phosphorylation. Similarly, AICAR incubation of isolated rat extensor digitorum longus (EDL) muscles did not increase p38 phosphorylation. Next, we used transgenic mice expressing an inactive form of the AMPKalpha2 catalytic subunit in skeletal muscle (AMPKalpha2i TG mice). AMPKalpha2i TG mice did not exhibit any defect in basal or contraction-induced p38 MAPK phosphorylation. We also used transgenic mice expressing an activating mutation in the AMPKgamma1 subunit (gamma1R70Q TG mice). Despite activated AMPK, basal p38 MAPK phosphorylation was not different between wild type and gamma1R70Q TG mice. In addition, muscle contraction-induced p38 MAPK phosphorylation was significantly blunted in the gamma1R70Q TG mice. In conclusion, increasing AMPK activity by AICAR and AMPKgamma1 mutation does not increase p38 MAPK phosphorylation in skeletal muscle. Furthermore, AMPKalpha2i TG mice lacking contraction-stimulated AMPK activity have normal p38 MAPK phosphorylation. These results suggest that p38 MAPK is not a downstream component of AMPK-mediated signaling in skeletal muscle.

To examine the role of muscle AMP-activated protein kinase (AMPK) in maximal exercise capacity, whole body glucose homeostasis, and glucose transport in skeletal muscle, we generated muscle-specific transgenic mice carrying cDNAs of inactive AMPK alpha2 (alpha2i TG). Fed blood glucose was slightly higher in alpha2i TG mice compared to wild type littermates, however, the difference was not statistically significant. In alpha2i TG mice, glucose tolerance was slightly impaired in male, but not in female mice, compared to wild type littermates. Maximal exercise capacity was dramatically reduced in alpha2i TG mice, suggesting that AMPK alpha2 has a critical role in skeletal muscle during exercise. We confirmed that known insulin-independent stimuli of glucose transport including mitochondrial respiration inhibition, hyperosmolarity, and muscle contraction increased both AMPK alpha1 and alpha2 activities in isolated EDL muscle in wild type mice. While, alpha2 activation was severely blunted and alpha1 activation was only slightly reduced in alpha2i TG mice by these insulin independent stimuli compared to wild type mice. Mitochondrial respiration inhibition-induced glucose transport was fully inhibited in isolated EDL muscles in alpha2i TG mice. However, contraction- or hyperosmolarity-induced glucose transport was nearly normal. These results suggest that AMPK alpha2 activation is essential for some, but not all insulin-independent glucose transport.