This paper studies the process scalability of pulse-mode CMOS circuits for analog 2-D convolution in computer vision systems. A simple, scalable architecture for an integrate and fire neuron is presented for implementing weighted addition of pulse-frequency modulated (PFM) signals. Sources of error are discussed and modeled in a detailed behavioral simulation and compared with equivalent transistor-level simulations. Next, the design of a 180-nm PFM chip with programmable weights is presented, and full image convolutions are demonstrated with the analog hardware. Preliminary chip measurements for a 45-nm implementation are also included to demonstrate process scalability. Design considerations for porting this architecture to nanometer processes, including FinFET technologies, are then discussed. This paper concludes with a simulation study on scaling down to 10 nm using a predictive technology model.

Computer vision algorithms are often limited in their application by the large amount of data that must be processed. Mammalian vision systems mitigate this high bandwidth requirement by prioritizing certain regions of the visual field with neural circuits that select the most salient regions. This work introduces a novel and computationally efficient visual saliency algorithm for performing this neuromorphic attention-based data reduction. The proposed algorithm has the added advantage that it is compatible with an analog CMOS design while still achieving comparable performance to existing state-of-the-art saliency algorithms. This compatibility allows for direct integration with the analog-to-digital conversion circuitry present in CMOS image sensors. This integration leads to power savings in the converter by quantizing only the salient pixels. Further system-level power savings are gained by reducing the amount of data that must be transmitted and processed in the digital domain. The analog CMOS compatible formulation relies on a pulse width (i.e., time mode) encoding of the pixel data that is compatible with pulse-mode imagers and slope based converters often used in imager designs. This letter begins by discussing this time-mode encoding for implementing neuromorphic architectures. Next, the proposed algorithm is derived. Hardware-oriented optimizations and modifications to this algorithm are proposed and discussed. Next, a metric for quantifying saliency accuracy is proposed, and simulation results of this metric are presented. Finally, an analog synthesis approach for a time-mode architecture is outlined, and postsynthesis transistor-level simulations that demonstrate functionality of an implementation in a modern CMOS process are discussed.

This paper presents an analog CMOS architecture for a visual saliency processor inspired by neuromorphic saliency algorithms. Time-mode computation is used to take advantage of the voltage-to-time conversion already present in many imager architectures so that the processor can be integrated directly into a CMOS imager. The architecture makes use of recent advances in time-mode computation, in particular the time-mode translinear principle, to realize the saliency algorithm with only pulse based computation. Simulation results are presented on a large image dataset, and a synthesis strategy is demonstrated. The circuit was implemented in a 45nm CMOS process, and post layout simulations are presented characterizing the circuit.

In this paper, we present a three-dimensional graphene foam made of few layers of CVD grown graphene as a scaffold for growing cardiac cells and recording their electrical activity. Our results show that graphene foam not only provides an excellent extra-cellular matrix (ECM) for the culture of such electrogenic cells but also enables recording of its extracellular electrical activity in-situ. Recording is possible due to graphene's excellent conductivity. In this paper, we present our results on the fabrication of the graphene scaffold and initial studies on the culture of cardiac cell lines such as HL-1 and recording of their real-time electrical activity.

This paper describes the implementation of a new architecture to multiply signals with time-mode representations. The exponential relationship between voltage and time in an RC circuit is utilized to implement time-mode logarithmic and exponential functions needed to realize a time-mode analog of the translinear principle. Addition of time-mode variables is achieved through the natural progression of time equal to the sum of the input times. By combining these two techniques, an analog multiplier can be implemented almost exclusively with passive circuits and digital primitives. Therefore, the circuit performance could benefit from CMOS scaling trends. A circuit level implementation in a 180nm CMOS process achieves 0.26% linearity error and consumes 9.5pJ per operation. Both behavioral and post layout simulation results are presented.

This work proposes a novel translinear principle based on time domain processing of signals. The exponential relationship between voltage and time in an RC circuit is exploited to implement a logarithmic voltage-to-time converter and an exponential time-to-voltage converter. These circuits are the time domain analogs of the voltage mode translinear circuits that exploit the exponential relationship between current and voltage in BJTs and subthreshold MOS transistors. Just as Kirchoff's voltage laws provide a natural form of addition for the voltage-mode translinear principle, the progression of time can also be a natural source of addition for the proposed time-mode analog of this principle. In this work a time-mode adder circuit is used to realize a translinear principle in time. This paper describes the theory behind this time-mode translinear principle. Furthermore, the design of nonlinear circuit functions, e.g., multiplication and power law, based on the time-mode translinear principle is described. Simulation and measurement results for a two-input single quadrant multiplier are presented. The chip was fabricated in a 180 nm CMOS process with simulation results agreeing closely with experimental results. We also present error analysis for such circuits and provide a brief discussion on future prospects of this approach.

A new architecture to multiply signals with time-mode representations is proposed. The exponential relationship between voltage and time in an RC circuit is utilised to implement the time-mode logarithmic and exponential functions needed to realise a time-mode analogue of the translinear principle. The addition of time-mode variables is achieved through the natural progression of time equal to the sum of the input times. By combining these two techniques, an analogue multiplier can be implemented almost exclusively with passive circuits and digital primitives. Therefore, the circuit performance could benefit from CMOS scaling trends. The architecture is described, and simulation results are presented for an operational circuit implementing this approach.

Analog computation traditionally processes information as differences in voltage or current amplitudes. With technology scaling resulting in reduced headroom and limited dynamic range, time-mode computation has emerged as a viable approach for low-power high-precision analog signal processing. Time mode circuits use differences in time to represent information. So far, only linear relationships between voltage/current and time has been explored for applications in data conversion, frequency synthesis and signal processing. In this paper, we present a time-mode analog of the well-known "translinear" principle using linear RC circuits and exploiting the exponential relationship between voltage and time for step charging or discharging of the capacitor. We present basic circuit analysis and utilize the technique to implement a simple single quadrant analog multiplier in an 180nm CMOS process. At 1.8V supply, the multiplier consumes approximately 5mW for a sampling frequency of 100kHz and a maximum input peak-to-peak voltage swing of 0.8V. The average non-linearity error is 0.44%. The time mode translinear principle could facilitate high dynamic range, high precision, complex linear and nonlinear arithmetic and other signal processing functions.

This paper presents the design and implementation of an analog-to-information converter (AIC) based on compressed sensing. The core of the AIC is an edge-triggered charge-sharing SAR ADC. Compressed sensing is achieved through random sampling and asynchronous successive approximation conversion using the ADC core. Implemented in 90nm CMOS, the prototype SAR ADC core achieves a maximum sample rate of 9.5MS/s, an ENOB of 9.3 bits, and consumes 550μW from a 1.2V supply. Measurement results of the compressed sensing AIC demonstrate effective sub-Nyquist random sampling and reconstruction of signals with sparse frequency support suitable for wideband spectrum sensing applications. When accounting for the increased input bandwidth compared to Nyquist, the AIC achieves an effective FOM of 10.2fJ/conversion-step.

Wireless physiological sensors are often limited by energy consumption of the hardware. Power consumption is typically related to the amount of data being transmitted, conventionally the Nyquist rate which is twice the bandwidth of the signal. However, if the signals are sparse in a known basis, compressed sensing facilitates accurate reconstruction of data when sampled below the Nyquist rate. Thus, power consumption at the sensor node could be improved, which would allow long-term use of wireless physiological sensors. We have implemented a random sampling based compressed analog to information converter (AIC) in 90nm CMOS technology. Sufficiently sparse signals were reconstructed using the ℓ1-minimization algorithm. Here we present experimental results that demonstrate reconstruction of non-sparse signals, in this case EEG, by using an ℓ1, 2 regularization algorithm exploiting group sparsity. These results demonstrate the performance achievable by physical compressed sensing AIC systems for brain computer interface applications.

Applications that require wireless wideband spectrum sensing are often limited by energy consumption of the sensing hardware. The power consumption is typically directly related to the amount of data transmitted. The emerging theory of compressed sensing provides a framework for reconstructing the sensed spectrum with fewer samples than are produced from Nyquist rate sampling. We have implemented a compressed sensing analog-to-information converter (AIC) in 90nm CMOS technology that allows complete reconstruction of a sparse spectrum consisting of discrete frequency bands. Typically, ℓ 1 -minimization based algorithms are used to reconstruct the original signal for compressed sensing. However, these algorithms do not perform well as signal sparsity decreases. This limitation can be mitigated by using ℓ 1,2 regularization based algorithms that exploit group sparsity. We present experimental results comparing the performance of both types of algorithms for reconstructing discrete frequency bands sampled with this AIC. These results demonstrate the performance achievable by physical AIC systems that utilize compressed sensing theory.