This paper presents an optically clocked 10 GS/s-sampler monolithically integrated in a photonic 0.25 μm SiGe-BiCMOS technology, which uses an ultra-stable optical pulse train generated by a hybrid mode-locked laser to sample an electrical signal. The integrated circuit includes optical waveguides, as well as a grating coupler, Germanium photodiodes with a bandwidth of >50 GHz, and an integrate-and-dump sampler. Experimental results demonstrate an analog bandwidth exceeding 30 GHz, a jitter of <30 fs, as well as a THD of <-33 dB over the entire bandwidth, and a SNR of 35.3 dB.

A novel monolithic opto-electronic clock converter integrated in a photonic SiGe-BiCMOS technology is presented, which turns an ultrashort optical pulse train generated by a hybrid mode-locked laser into a low-jitter electrical square wave with sharp transitions. The integrated circuit includes optical waveguides as well as grating couplers, a high-bandwidth (> 30 GHz) Ge-photodiode, a frequency divider-by-two implemented by SiGe bipolar transistors, photodiode characterization circuits and an optical monitoring path. The integrated circuit has been successfully tested at laser pulse repetition rates of up to 10 GHz. At this pulse repetition rate, the generated 5 GHz electrical square wave signal features a wideband phase noise floor <;-160 dBc/Hz and an jitter tj <; 1 fs while integrating the phase noise at offset frequencies between 2 kHz and 30 MHz.

A transimpedance amplifier (TIA) in 1-μm InP technology for the application in next generation fiber optical data communication systems is presented. The TIA exhibits a bandwidth of 45 GHz, a differential transimpedance of 70dBOhm and a total harmonic distortion (THD) below -30 dB up to a differential output voltage of 500mV-PP.

In 2010, the standard for 100GbE was approved, which specifies the transmission of 100 Gb/s via 4 wavelength channels of 25 Gb/s each. A solution based on a 100 Gb/s single wavelength channel is capable of significant cost reductions should the required components be available. Within the HECTO project, we developed components suitable for single-wavelength 100 Gb/s transmission. In this article, the project is described - its organization, objectives, possible impacts, and results - including the successful demonstration in a final field trial. A complete ETDM system utilizing the monolithically integrated transmitter and receiver modules developed in the project was built to transmit 112 Gb/s over 42 km standard single-mode fiber. Finally, we attempt an outlook on the prospective development of Ethernet standardization beyond 100GbE.

A novel architecture of a track and hold (T&H) circuit for the realization of a high speed analog demultiplexer is presented in InP DHBT Technology. The architecture allows a sampling rate flexible demultiplexing of an analog input signal. The demultiplexer features a measured THD above 32 dB and a SFDR above 35 dB with a differential input voltage of 0.5V-PP when operating at 25 GHz. This allows the realization of a 50 GS/s analog-to-digital conversion system.

Traditional intensity modulated two-level electrical time-division multiplexing（ETDM）transmission systems working at 100-112Gbit/s were investigated.The complete ETDM systems based on monolithically integrated transmitter and receiver modules were demonstrated with bit-error-rate（BER）performance of 10-8 at 107Gbit/s,and near error-free standard forward error correction（FEC）threshold（2×10-3）at 112Gbit/s.The experiment results showed that directly modulated high-speed ETDM transmission systems with the symbol rates at 100Gbaud and beyond were promising candidate for cost-effective 100GbE applications and might be a preform of the next generation of Terabit/s Ethernet.

A method for improving the sensitivity (or speed) of a master-slave emitter-coupled logic comparator using emitter degeneration resistors is presented. The degeneration resistors in the latching pair reduce the transistor charging time, thus allowing more time for regeneration. Improved and standard comparators were implemented using the InP/GaInAs heterojunction bipolar transistor technology and were tested at a clock rate of 20 GHz. The improved comparator exhibited better sensitivity (by a factor of 1.7) compared to the standard design. A record low-sensitivity value of 10 mV was obtained.

Continuous time delta-sigma (CTΔΣ) analog-to-digital converters (ADCs) are capable of sampling at much higher rates than discrete time ΔΣ converters. This makes heterojunction bipolar transistor (HBT) technologies excellent candidates for the implementation of fast CTΔΣ ADCs. Due to linearity considerations, all HBT-based ΔΣ ADCs known to us incorporated a single-bit digital-to-analog converter (DAC). Here, we present a multibit lowpass ΔΣ ADC based upon the InP HBT technology, which incorporates an internal resolution of 2 bits. The ADC was clocked at 10 GHz, its total power consumption was 1.9 W, and it obtained a signal-to-noise ratio (SNR) of 44.1 dB at signal bandwidth of 312.5 MHz.

This letter reports the potential of an InP-based double-heterojunction bipolar transistor (DHBT) using a thin highly doped n+-InP layer inserted at the base-collector junction. Molecular-beam-epitaxy-grown abrupt pulse-doped InP-InGaAs-InP DHBTs ensure very high current gains of ~ 90, low saturation voltages of less than 1 V, and high cutoff frequencies of ~ 350 GHz. Using this technology, a compact high-speed high-voltage multiplexer-driver integrated circuit (IC) suitable for high-speed signal processing and communication systems has been designed and fabricated. The IC has successfully been measured at 112 Gb/s with very clear eye openings of up to 2 Vpp with a power consumption of 2 W.

It is now clear that 112-Gb/s data rate is the next step in the network evolution (100-Gb/s Ethernet). Due to its high speed and high breakdown voltage, the InP double-heterojunction bipolar transistor (DHBT) technology is particularly suited for signal processing and high-speed communication systems. This paper summarizes our InP DHBT device and integrated circuit (IC) technology developed for >; 100-Gb/s-class medium scale mixed-signal ICs. Key features and issues important for the growth and manufacturing of InP DHBTs with step-graded collectors are first discussed. The molecular-beam-epitaxy-grown transistors have cut-off frequencies (f T and f max ) of over 350 GHz, current gains of ~90, and common-emitter breakdown voltages of >; 4.5 V. Using this technology, we then fabricated and succeeded in 112-Gb/s testing of multiplexers and integrated clock and data recovery/1:2 demultiplexer ICs and modules with very clear eye waveforms. Using the same technology, a distributed amplifier intended for use as a modulator driver exhibited an output voltage swing of ~2 V pp . These building-block ICs combine high-speed operation with high signal quality and enable 112-Gb/s optical fiber transmission.

Key components and architecture options are being actively investigated to realize next generation transport technology in optical networks. Serial transmission systems using a single wavelength have, so far, provided cost effective solutions and therefore remain desirable. For 100 Gbit/s Ethernet, this option will, however, depend on the availability of the electronic and optical components. Due to its high speed and high breakdown voltage, the InP double-heterojunction bipolar transistor (DHBT) technology is particularly suited for signal processing and high-speed communication systems. This contribution describes our InP DHBT based integrated circuit (IC) technology developed for 100 Gbit/s class mixed-signal ICs. Using this technology, we fabricated and succeeded in 112 Gbit/s testing of key electronic components, including a multiplexer (MUX), a distributed amplifier, and an integrated clock and data recovery (CDR)/1:2 demultiplexer (DEMUX), with very clear eye waveforms. These high-speed building block ICs are described and the main results are presented.

We present a high linearity 2-bit digital-to-analog converter (DAC) implemented in an InP/GaInAs DHBT technology. The DAC is based upon the current steering architecture. Cascode structure and layout techniques, i.e. static shuffling and dummy devices, have been used to enhance the linearity. The DAC exhibits static integral/differential nonlinearities of 5.5 × 10 -3 LSB, equivalent to a resolution of 9.2 bits. Dynamic measurements qualitatively show proper behavior at 6 GS/s, while simulations with typical on-chip load exhibit sufficiently fast settling at 20 GS/s.

Components of a 100 Gb/s transmitter with electrical time-division multiplexing are presented as following: electrical multiplexer, driver amplifier, and large-bandwidth distributed feedback-traveling-wave electro-absorption modulator module. The performance of the parts of the transmitter, as well as the complete chain, is investigated for data operation and transmission in future 100 Gb/s Ethernet (100GbE). Clearly open eye diagrams at 100 Gb/s are demonstrated together with data transmission over 300 m long standard single mode fiber link.

A high-speed pin-TWA photoreceiver, comprising a photodiode and a travelling-wave amplifier, monolithically integrated on a single InP chip, are characterized in OOK system experiments. Error-free performance below the FEC limit is achieved in back-to-back measurements up to 112 Gb/s.

112 Gb/s field trial demonstration of a complete ETDM system based on monolithically integrated transmitter and receiver modules was achieved for the first time, with BER performance below FEC error-free threshold at 2(31)-1 PRBS tributary data word-length.

The development of transmission technology for 100G long-haul transmission systems is mainly concentrated on systems with low symbol rate (up to about 50 Gbaud) in conjunction with higher-order modulation formats (e.g. QPSK) and coherent detection. These systems provide a high spectral efficiency and robustness against transmission impairments. For short-reach systems or future long-haul systems with higher data rates (400 Gb/s or above), the use of higher symbol rates (100 Gbaud or higher) is of interest. Such systems have comparably simple transmitter and receiver architectures, which could result in cost-efficient realizations. However, this is only true if compact and integrated solutions for the key-components (optical-to-electrical-, electrical-to-optical-conversion, electrical amplification and processing) are found at such high symbol rates. Within the European funded projects HECTO and GIBON, such key-components, based on InP technology, have been realized over the past 3 to 3.5 years. In this paper, we report on the application of the InP-based components developed in HECTO and GIBON, in particular the receiver components, in system experiments up to 112 Gb/s OOK. The investigated components are: 1) a high-speed photoreceiver (up to 112 Gb/s), comprising a photodiode and a traveling-wave amplifier, monolithically integrated on a single chip; 2) a bias-feeding photodetector with high bandwidth (90 GHz), which can be adapted to the subsequent electronic components by a variable output DC level and 3) a CDR-module, developed by the Fraunhofer IAF, which enables simultaneous electrical 1:2 demultiplexing and clock recovery up to 112 Gb/s. We show measurements of eye diagrams and bit error ratios up to 112 Gb/s.

This paper presents a monolithically integrated clock and data recovery (CDR) circuit with 1: 2 demultiplexer (DEMUX), which is capable of processing signals with data rates between 107 Gbit/s and 112 Gbit/s. The fabrication of the integrated circuit (IC) relies on an in-house InP double heterostructure bipolar transistor technology (DHBT) featuring cut-off frequency values of more than 350 GHz for both f(T) and f(max). The CDR concept is based on a half-rate circuit architecture, whose main components are a linear phase detector including a 1: 2 DEMUX, a voltage controlled oscillator (VCO), and a loop filter. Mounted into a module, the CDR/1:2 DEMUX features proper operation at data rates up to 112 Gbit/s, whereas the recovered and demultiplexed data exhibit clear eye opening and a voltage swing of 500 mV(pp). The half-rate clock signal extracted from the input data features a voltage swing of 250 mV(pp). By using the CDR module in an optical system environment, a bit error rate (BER) well below 10(-10) is obtained at 112 Gbit/s with a data word length ranging up to 2(31)-1.

We present simulations and measurements of the sensitivity of a master-slave emitter-coupled logic (ECL) latched comparator implemented in an InP/GaInAs DHBT technology. The circuit exhibited simulated and experimental sensitivities of 11.5 mV and 17 mV, respectively, at a clock rate of 20 GHz, with no preamplifier.

Performance of a packaged distributed-feedback travelling-wave electroabsorption modulator module for data transmission at 100 Gb/s is presented for the first time. Clearly open eye diagrams at 80 Gb/s with an extinction ratio ( ER) of 4.9 dB and 100 Gb/s with ER 4.2 dB ( limited by measurement setup) are demonstrated together with data transmission over 100-m-long standard single-mode fiber and over dispersion-compensated 10-km fiber link.

Electro-Absorption-Transceiver (EAT) structures used as efficient Travelling-Wave Electro-Absorption-Modulator (TWEAM) as well as Travelling-Wave-Photo-Detector (TWPD) are investigated. Clear eye-openings at 100 Gb/s for operation as modulator and/or as detector, as well as 80 Gb/s transmission between a pair of EATs, are presented.