In this study, a range of miniaturized Ag/AgCl reference electrodes with various layouts were successfully fabricated on wafer-level silicon-based substrates with metallic intermediate layers by precisely controlling the electrochemical deposition of Ag, followed by electrochemical chlorination of the deposited Ag layer. The structure, as well as the chemical composition of the electrode, were characterized with SEM & EDS. The results showed that the chlorination is very sensitive to the applied electric field and background solution. Potentiostatic chlorination, in combination with an adjusted mushroom-shaped Ag sealing deposition, enabled the formation of electrochemical usable Ag/AgCl layers. The stability of the electrodes was tested using open circuit potential (OCP) measurement. The results showed that the reference electrodes stayed stable for 300 s under 3 M KCl solution. The first stage study showed that the stability of the Ag/AgCl reference electrode in a chip highly depends on chip size design, chlorination conditions, and a further protection layer.

In this contribution we present an approach upon process window evaluation based on different STI test chip designs. General applicable process rules are derived, which help IC design engineers to care for key process requirements of CMP without full process insights. Special focus is laid on the sensitivity of the polish process result in structured areas on surrounding densities as well as the impact of large regions with homogenous density e.g. pure field regions. In a case study we will present the application of these general results derived from test chip experiments to a designers demand. The change of STI density was highly desirable from a device point of view, but limited by design rules. Such design rules are often very strict to ensure a safe fabrication, however for device diversification the existing rules might be too strict. To work with (exceptions from) such strict design rules a detailed process understanding is needed. Based on test chip experiments design scenarios to avoid device problems due to CMP process restrictions have been derived.

There are numerous voltammetric and amperometric analysis methods to determine various parameters of an analyte solution. Depending on the electrochemical measuring principle, the number, positioning, material and area of the electrodes used are of particular importance. Noble metals such as gold or platinum are widely used as working electrodes, while a Ag/AgCl/KCl-based electrode is typically used as the reference electrode. In practice, conventional electrodes and electrode arrangements have considerable disadvantages. On the one hand, the costs of materials are high, because precious metal sheets or wires are widely used as electrodes. On the other hand, wetting of the electrodes needs to be ensured, which means that 20 ml or more of analyte is required, depending on the measuring arrangement. The aim of this work was therefore to manufacture and arrange accurate electrodes with the lowest amount of used precious metals as possible in order to enable typical electrochemical measuring methods with a reliable and reproducible setup. The goal was not only to minimize the amount of precious metals for electrodes, but also to reduce the amount of analyte to one drop, i.e. to about 30 mul. At the same time, the resulting measuring component should be easy to handle and to use, both in aqueous media and in organic solvents.

A novel metallization for vertical integration in microsystems technology using through-silicon-via (TSV) was investigated. Cobalt metal-organic chemical vapor deposition (Co-MOCVD) process is capable of forming an excellent conformal ultra-thin film with good adhesion to the copper conductive and diffusion barrier layers. Co layer as a seed layer provides a direct copper electrochemical deposition (Cu-ECD). The main challenge of this metallization module is to reduce Co corrosion under the influence of Cu electrolyte. Based on the experimental results, the optimized deposition recipes have been obtained and discussed by varying the ECD parameters, and characterizing the deposited films. Thereby, the Co corrosion was minimized even for the ultra-thin film of 5 nm. Metallization processes were performed on blank and structured samples (on both coupons and 300 mm wafers). Barrier films stack deposition and in-vacua annealing were carried out without breaking the vacuum in the 300 mm cluster tool. Afterwards, ECD processes were accomplished on coupon level in a lab-scale plating cell. Moreover, different metrology, ex-situ characterizations and measurements were performed by time-of-flight secondary ion mass spectroscopy (ToF-SIMS), transmission electron microscopy (TEM), cross sectional scanning electron microscopy (XSEM) and x-ray reflectometry (XRR), for revealing thickness loss, corrosion percentage and elemental depth profile.

In the electrochemical deposition of copper on structured substrates, additives are commonly used as ingredients to refine the copper thin film properties. By means of cyclovoltametric (CV) measurements, we examine the process behavior of the additives PEG (polyethylene glycol) and chloride ions over a wide range of experimental parameters relevant for production-like conditions. In this plating process, additives practically are neither consumed in chemical reactions nor are they incorporated into the growing copper film. To understand the observed complex hysteresis behavior of the deposition current in CV scans, we have recently proposed a model which is able to qualitatively explain this behavior without supposing additive consumption. In the present study, we fit crucial parameters of this model from the experimental data to increase its predictive power. The quantitative agreement of performed simulations of CV scans with the measured scans demonstrates the validity of the proposed copper deposition model. Equipped with the determined parameter set, the model can help to optimize the copper plating process in industrial applications. (C) 2018 The Electrochemical Society.

Additives play an important role in electrochemical deposition and understanding their working mechanism is a great challenge. In cyclic voltammetry measurements of copper deposition, a complex hysteresis behavior is ubiquitously observed. In previous models a common assumption to explain the hysteresis is the consumption of additives during copper deposition. However, second-ion mass spectrometry measurements often detected comparatively low levels of impurities in deposits. We proposed recently an alternative mechanism for explaining hysteresis without invoking additive consumption. By assuming for instance a conformation change in the adsorbed PEG layer and an additional activation of additive desorption by copper deposition, the new model can reproduce characteristic features of cyclic voltammograms measured under vastly different conditions and exhibiting pronounced hysteresis. In parallel to that, we examined experimentally the process behavior of the additives PEG (polyethylene glycol) and chloride ions over a wide range of parameters relevant for production-like conditions. Moreover, we fitted crucial parameters of our model from the experimental data. The quantitative agreement of performed simulations of CV scans with the measured scans demonstrates the quantitative predicting power of the proposed model. Equipped with the determined parameter set, the model may help to optimize the copper plating process in industrial applications.

In this paper we discuss the different behaviors of four state-of-the-art post CMP cleaning chemistries with respect to cleaning performance, wafer surface properties and electrical performance. The wafer surface properties include roughness and material composition evaluation. In addition to the commonly done investigation of the cleaning performance of the chemistries, analysis like XPS and SEM of post CMP wafer surfaces were performed and a correlation between the properties of the chemistry and the resulting wafer properties is discussed. A significant difference in the kind of carbon bonding on the Cu surface as well as the resulting sulfur residues on the wafers were observed for the different chemistries that were tested. Furthermore, stress tests of the Cu surface revealed different etch damages for the different chemistries. It is also shown that the interaction of cleaning chemistry with wafer surface can cause a decrease in the breakdown voltage inside the BEoL stack. Finally, a comparison of the advantages and disadvantages of the tested chemistries is given and in conclusion, the identified properties of each chemistry are assessed with regard to manufacturability. Keywords: Chemical-mechanical polishing, Post CMP clean, Wafer cleaning, Surface analysis, Electrical performance, Breakdown voltage, 22 nm FD-SOI

The proceeding scaling inmicroelectronic devices requires smaller and smaller copper wires for energy transfer in integrated devices. Voids in the copper wires lead to a resistance increase and damage of the wiring. Copper wires are fabricated by electrochemical deposition as it enables a bottom-up, void free copper growth, so-called superfilling. The present work focuses on the mechanism of the electrochemical deposition with the goal of understanding and describing the superfilling. Electrochemical measurements and partial fill experiments under production-like conditions are carried out to study the effects of bath additives. The co-adsorption theory is adopted to explain additive interaction which is presumed to be the key for superfilling. It is shown that superfilling is a result of the synergetic adsorption behavior of at least two organic additives and a kinetic balancing between additive accumulation and copper deposition rate. (C) The Author(s) 2016. Published by ECS. All rights reserved.

The advanced scaling in microelectronic devices requires filling of smaller and smaller copper lines without the introduction of voids and defects. Electrochemical deposition is the process of choice as it ensures a bottom-up, void-free copper growth, so-called superfilling. The present work focuses on the mechanism of superfilling based on additive co-adsorption principles. These principles describe the formation of a complex and reversible adsorption layer of two interacting surface active substances [1]. While positive interaction causes enhanced adsorption and increased surface coverage, negative interaction results in inhibited adsorption and lower surface coverage (Figure 1). The co-adsorption theory is adopted to explain the functioning of plating additives which is presumed to be the key for superfilling. Electrochemical measurements and partial fill experiments under production-like conditions are carried out to study the effects of bath additives in sub-100 nm structures. It is shown that superfilling is a result of the synergetic adsorption behavior of two organic additives, accelerator and suppressor, and a balancing between additive accumulation and copper deposition rate. During copper deposition both additives accelerator and suppressor accumulate near the growing surface. Due to diffusion limitations inside narrow features, a higher additive concentration evolves compared to blank surface areas. If the deposition proceeds at a high rate, the different additive concentrations inside and outside small features can be used to achieve superfilling (Figure 2). References [1] B. B. Damaskin, V. A. Safonov, O. A. Baturina, and N. V. Safonov, J. Electroanal. Chem., 550–551, 3 (2003). Figure 1

Advanced liner materials are crucial for optimizing and further shrinking of integrated circuits' interconnects. For next generation devices there is a focus on Cobalt (Co) and Ruthenium (Ru) [1]. Besides the challenges to deposit such materials, new chemical-mechanical polishing (CMP) process compatibility is needed. Especially Co introduces a bunch of new requirements. To reach the advantages of improved step coverage and lowered electrical resistivity compared to Tantalum nitride (TaN) [2] a complete change in consumables is needed to prevent Co from corrosion. Different CMP consumables are tested in a newly established 28 nm Co integration flow with special focus on corrosion properties and electrical performance. Starting from a standard TaN/Ta barrier process the corresponding consumables are systematically changed from non- Co compatible to Co compatible alternatives. Eventually the polishing steps are tuned to meet the integration requirements.