A 25 V ESD NPN transistor is made high current capable by means of distributed emitter ballasting. The proposed segmentation of the emitter contact area along the width offers an efficient way to extend the homogeneous current regime without causing any significant increase of the holding voltage. At high current, a second snap-back is observed in the TLP current-voltage characteristics. Transient interferometric mapping analyses show that this voltage drop is due to current filamentation arising at a time decreasing with increasing current amplitude

An unexpected and serious effect from the ESD HBM tester causing gate oxide failure in input buffers is reported in this paper. The most significant finding is that this unwarranted stress comes from the tester relay and gives rise to false HBM evaluation. In this paper we investigate this new effect on gate oxide reliability and establish the safe control limits for proper output of the state-of-the-art ESD simulator waveforms.

An integrated lateral output device is presented which has a very high degree of ESD robustness. The high ESD robustness is achieved with negligible increase in the overall size of the output device. Such an integrated device is ideally suited for high voltage output pins requiring low on-state resistance (Rdson) with stringent system level IEC requirements.

Conflicting HBM ESD results are presented for several ESD testers/test-configurations, all of which pass the present tester specifications. The discrepancy is attributed to parasitic capacitance, which can deactivate the dV/dt-detection of an ESD circuit. An unexpectedly large (>1 nF) effective parallel capacitance is found by summing tester relay capacitances of unstressed pins, connected through on-chip current paths, while considering the Miller effect. An ESD strike between two pins and the symmetric "reverse-pin, reverse-polarity" strike are shown to be nonequivalent due to a different set of on-chip current paths.

A new pseudo-vertical integrated npn bipolar transistor with variable sustaining and trigger voltages is presented in this paper. It is shown that the sustaining voltage can be tuned to obtain the required high value. These devices are realized in a junction isolated (JI) mixed-signal power BiCMOS technology with maximum breakdown voltage requirements in excess of 60V. The ESD robustness of these bipolar transistors is verified using transmission line pulse (TLP) and HBM (human body model) measurements. It is now possible to use a single bipolar transistor as an ESD protection device for a high voltage pin application instead of using stacked bipolar devices. The net result is a better control and possible reduction in overall die area.

A novel 2D-simulation method is used to simulate major aspects of the formation of the current filament and to help understand and predict the level of ESD robustness in lateral power devices

Safe operating area limits for large Ldmos are shown to be due to a thermal instability mechanism initiated by avalanche generated carriers which turn-on the parasitic bipolar transistor. An analytic model is described and is shown to agree well with experimental data.

A simple method for demonstrating filamentation in lateral power devices is described. The results show that "mathematically perfect" junctions need to have defects added to initiate filamentation. When this is done, two-dimensional simulations exhibit behavior that is seen in practice. One application of these results is the design of protection structures