A peculiar temperature mismatch between a power LDMOS and its sense FET develops over time resulting in yield losses. The anomaly is traced to trapped charge in the power LDMOS that arises from a seemingly unrelated change in the hydrogen anneal temperature in the back end. The physical mechanism leading to the anomaly and the interaction between temperature mismatch and metal layout are presented.

This work reviews common motor types, driving methods, and associated requirements of power LDMOS drivers including BVdss, Rdson, and SOA for peripheral product applications up to 60 V. Tradeoffs made between various processes, power efficiency, and circuit implementations are discussed. The paper explores additional motor driving specific concerns such as substrate injection, parasitic npn/pnp effects and robustness, reverse recovery, and ESD. Up integration concerns and sensitive circuit isolation techniques are also included. The introduction includes a short process technology outline for peripheral product power ICs (PICs).

A novel 2D-simulation method is used to simulate major aspects of the formation of the current filament and to help understand and predict the level of ESD robustness in lateral power devices

A simple method for demonstrating filamentation in lateral power devices is described. The results show that "mathematically perfect" junctions need to have defects added to initiate filamentation. When this is done, two-dimensional simulations exhibit behavior that is seen in practice. One application of these results is the design of protection structures

Technology is driven by the evolving CMOS roadmap, and as a consequence, it is increasingly difficult to integrate high performance bipolar devices without unduly increasing process complexity. Designers want and need good NPN devices for key circuits; a table of some of these is outlined. Bipolar device needs and the difficulties of device performance vs. integration are described for typical advanced power BiCMOS technology with respect to design concerns. Other bipolar issues relating to guard-ring, parasitics, and ESD concerns are also briefly discussed.

A novel lateral power device structure with a very high degree of ESD (electrostatic discharge) robustness is presented. This device called the SCR-LDMOS is modification of the lateral LDMOSFET with good on state and blocking characteristics.