Chiplet technology for 2.5-D/3-D integration is being rapidly adopted, including in mission critical applications. We present a study of the radiation sensitivity of a prototype Advanced Interface Bus (AIB) chiplet die-to-die interface in 28 nm fully depleted silicon on insulator (FD-SOI) technology. The single event effect (SEE) sensitivity was evaluated first using fault injection simulations, and these results were compared with those obtained using alpha particles and a pulsed laser, which enabled us to identify the most sensitive regions. Due to the large number of flip-flops in the interface, there is a significant cross section, although the majority of faults manifest themselves as single-bit data-upsets. The effect of the dose deposited by the alpha particles was also studied.

In advanced technology nodes, the number of factors that influence the soft error rate (SER) is steadily increasing. In order to effectively address these evolving challenges, transport models for the simulation of soft errors must undergo corresponding enhancements. In this work, a fast 3D Poisson equation solver that has been optimized for FinFET architectures has been integrated into the Tool Suite for rAdiation Reliability Assessment (TIARA) simulation platform. The SEU predictions on 3nm FinFET D-flip-flops exposed to heavy ions are made and compared with experiments. A detailed analysis of the spatial distribution of radiation-induced errors predicted by the model is conducted to provide information on the radiation hardness assurance and hardening at this node of technology.

Hardware implementations of cryptographic algorithms are vulnerable to physical injection attacks which can lead to Differential Fault Analysis (DFA) or round-skipping attacks. While formal verification is a powerful technique to analyze security, existing methods struggle with efficiency and precision. Traditional equivalence checking tends to generate a vast number of irrelevant counter-examples, requiring extensive post-processing to identify exploitable faults and slowing down the verification process. Furthermore, crafting precise properties for complex countermeasures is difficult and not portable across different designs. We introduce a novel fault model-driven formal verification methodology that shifts this paradigm. By comparing the design against a faulty model reproducing a specific attack vector, our approach transforms the verification goal from finding any deviation to only finding faults that replicate a known, successful attack. This approach is then demonstrated on an AES design protected by parity-based countermeasures, using both classical DFA and round-skipping attacks, showing a significant reduction in verification time and counter-example volume compared to previous equivalence checking methods, with a reduction of proof time by up to 92% and in the number of counter-examples found by a factor of $\mathbf{4 4}$, while additionally enabling the analysis of fault multiplicities up to 3. We further demonstrate the method’s versatility by applying it to DFA on a lockstep-protected PRINCE lightweight block cipher.

Simulation of the radiation response of advanced 3D CMOS technologies, such as FinFET and Gate-all-around technologies, requires more expressive charge transport and collection models. This is necessary to adapt to complex geometries, while keeping computational efficiency suitable for industrial Monte-Carlo workloads. In this work, the ambipolar diffusion with a-cutoff (ADC) model is reviewed and identified as a suitable candidate for such purpose. For the first time, a practical implementation able to simulate seamlessly complex and various standard cells is proposed. This refined model is then integrated in the industrial Monte-Carlo simulator TIARA and applied to 3nm FinFET flip-flop designs. Charge collection mechanisms in FinFET are discussed, along with the influence of process and design features, including comparison between FinFET generations.

The semiconductor industry is adopting chiplets as an alternative to integrated circuit design. With adoption of off-the-shelf chiplets, supply chain attacks are likely to increase, making chiplet authentication essential. This work identifies post-stacking testing as the best phase for authentication and proposes a framework using existing industry standards. The framework includes a flexible authentication IP integrated into the chiplet design, compatible with various authentication methods; an IP insertion flow compatible with commercial DFT insertion tools; a secure module for the test environment; and the corresponding test procedure. Results show that chiplet authentication can be implemented without disrupting industry practices, with multiple authentication methods available based on the context.

Recently, Machine Learning (ML) methods have demonstrated that accurate post-route metric prediction can accelerate design space exploration by eliminating time consuming place and route (PnR) iterations. However, there has been limited effort in exploring the capabilities of ML to leverage hierarchical predictions in performance estimation. We propose a hierarchical Graph Neural Network (GNN) architecture that exploits the fundamental causal relationship between timing and power consumption in digital circuits. Unlike existing approaches that treat these metrics independently, our two stage model first predicts timing characteristics, then leverages these predictions to enhance power estimation accuracy. Trained and evaluated on 20 designs ranging from 1K to 150k gates in SkyWater 130nm technology, our approach achieves 7.3% mean absolute percentage error (MAPE) for timing and 4.32% for power predictions. The hierarchical structure enables a significant speedup compared to commercial PnR tools while maintaining prediction fidelity, allowing designers to explore design variants in an efficient manner.

The integration of AES cores into safety-critical systems requires mechanisms that satisfy both functional safety (ISO 26262) and security requirements. However, protection schemes designed for laser fault injection (LFI), such as parity-based countermeasures, often exhibit high sensitivity to perturbations, triggering alarms on faults that are architecturally masked. These functional safety "false-positives" degrade system availability by forcing unnecessary recovery actions. ClassifyFP is a lightweight hardware fault classifier designed to filter false-positives in-situ to enable optimized system-level recovery strategies. Leveraging data from RTL fault injection campaigns on a LFI-robust serial AES-128 design, a decision tree is trained to distinguish between dangerous and safe parity violations based on temporal and spatial error patterns. Evaluated on 28nm FD-SOI technology, ClassifyFP reduces the false-positive rate from 67.76% to as low as 8.49% with an overhead of 11%, while preserving original security detection and safety coverage of dangerous faults.

This paper introduces a novel and efficient formal fault injection methodology for evaluating the fault tolerance of control-flow dominated digital blocks. By combining simulation with model checking, the approach leverages the strengths of both techniques to perform exhaustive and automated vulnerability analysis, on chosen functional modes of these IPs. A reference finite-state machine (FSM) is extracted from simulation to represent the nominal behavior of the circuit and is then partitioned into specific functional modes and phases. Fault injection is performed by mutating the circuit netlist and applying temporal properties to detect specification violations through assertion failures. The methodology supports both single and multiple-bit upsets, and provides accurate fault-tolerance metrics over time. Experimental results on industrial RISC-V IP blocks, specifically SPI and DMA controllers, demonstrate significant improvements in detection accuracy and runtime—achieving up to 696× speedup over traditional simulation-based fault injection. We believe that this formal framework enables scalable, reproducible, and rigorous fault analysis, paving the way for future extensions toward full-chip formal FMEA and hardware security validation.

With the increase in cybersecurity requirements and the growing connectivity of critical systems like vehicles and satellites, implementing both functional safety and hardware security is crucial. Although safety and security methods are well studied, combined analysis at the RTL or Netlist level remains under-explored. This paper provides an initial analysis of multiple AES designs—one unprotected, one with a safety-oriented countermeasure (Lockstep), and one with security-oriented countermeasures (Parity-Predictor)—using both simulation and formal methods. We identify the challenges and opportunities for enhancing combined safety and security assessments. Additionally, we evaluate the AES designs against ISO 26262 safety metrics and analyze their resilience to laser attacks, offering insight into their security robustness.

With the increasing availability of computational resources and the progress in research concerning automated formal methods, the characterization of safety features for hardware requires improved precision in functional vulnerability detection. In the context of formal fault injection, the model checking algorithm can be used to detect vulnerabilities in digital systems by violating the nominal temporal properties. We present a general methodology to reduce the state space that is computed and traversed during these fault campaigns. The chosen criteria preserves the nominal behavior and the failure modes, expressed by the fault-violated properties. This process is crucial to provide a manipulable object for subsequent Failure Mode and Effects Analysis. Finally, we propose an assumption-based guarantee technique to model how a fault may propagate through different hardware units, for a scalable methodology of formal fault injection and vulnerability detection in complex SoCs.

Chiplet-based chips are the natural evolution of traditional 2D SoCs. In the future, off-the-shelf chiplets are expected to represent an important component of the semiconductor industry. The IEEE Std 1838(TM)-2019 design-for-testability (DFT) standard enable testing of stacked chiplets from multiple vendors. However, the shared DFT network threatens the confidentiality and integrity of test data and other sensitive information. This paper addresses the security concerns associated with DFT infrastructures in chiplet-based systems. We discuss the necessity of securing DFT infrastructures to prevent unauthorized access and malicious activities. Furthermore, we propose a hardware countermeasure that combines encryption and encoding to secure communication over the DFT network. Results show that the DFT can be protected from misbehavior from malicious chiplets on the stack, scan-based attacks, and brute force attacks with minimal overhead in terms of area and test time. The proposed solution causes less than 1% area overhead on designs composed of more than 5 million gates and less than 1% test time overhead for typical DFT implementations.

We performed soft error rate (SER) characterization of 40-and 65-nm bulk CMOS static random access memories (SRAMs) combined with neutron spectrometry in the deuterium-tritium (D-T)-fueled Joint European Torus (JET) tokamak during its final D-T plasma operation (September and October 2023) producing a series of several dozens of power pulses. Our experimental results demonstrate the impact of machine operation on the electronics' reliability, emulating realistic conditions for circuits exposed to the partially radiation-shielded environment of future fusion reactors. Typical bit-flip (BF) rates of 493 h(-1)Gbit(-1) for 65-nm SRAMs and 2342 h(-1)Gbit(-1) for 40-nm SRAMs were measured for a residual machine-induced neutron flux of similar to 3.15 x 10(5) cm(-2)s(-1) below the reinforced concrete slab (thickness of 1045 mm) supporting the tokamak chamber. To complete this characterization work, a general methodology for the SER prediction in such a mixed-field D-T neutron radiation environment composed of both thermal and fast neutrons (FN) (up to 14 MeV) is presented and validated from this ensemble of experimental data for the two SRAM technologies. Finally, the interest in this approach for future tokamaks and high-energy physics accelerators is discussed.

Chiplet technology for 2.5-D/3-D integration is being rapidly adopted, including for System-on-Chips used in mission critical applications. We present a Total Ionizing Dose Effect study of a prototype Advanced Interface Bus (AIB) die-to-die interface in 28nm FD-SOI technology using pulsed x-rays and in-situ monitoring of the dose. Degradation of the maximum working frequency of the interface was observed due to the deposited dose. Using either the core voltage or the body bias voltage, we demonstrate that it is possible to partially recover this frequency loss. In space applications, this compensation, combined with in-situ dose monitoring, can be used to extend the life of 2.5-D/3-D circuits using high-speed die-to-die interfaces.

Analog IP design encompasses a wide range of Analog Mixed Signal blocks of varied and different specifications. Ensuring reliability of Analog IPs on silicon is thus a challenging task, considering standard device-level reliability coverage may not cover all performances and specifications for Analog IPs. To master this, the use of dedicated Analog Qualification test vehicles (AQTV) is required. This understanding aids in optimizing the design and process (silicon) to attain the preferred balance between performance and reliability needs. In this paper, a workflow is proposed for Qualification of Analog Test Vehicles under High Temperature Operating Life (HTOL) conditions. This AQTV involves multiple IP: GPIOs, digRF, PLL, Oscillator, Compensation, I2C in P28 technology in single chip. Additionally, improvements are suggested to the test and design environments to proactively address future challenges. This industrial proactive approach not only leads to a more efficient reliability methodology with fewer iterations, but also reduces the cost of development and test for standard analog ICs. This approach aims to optimize time while presenting test results from a practical case as an initial step towards developing an efficient qualification methodology. To ensure consistency, test results are cross-verified using cad simulation by recreating a measurement setup similar to the test environment for a direct comparison between the measurement and simulation results.

This study focuses on the displacement damage-induced dark current and random telegraph signal (RTS) in the STMicroelectronics p-type photogate, a device moving away from the 4T pinned-photodiode (PPD), with a sensitive volume exclusively made of boron-doped p-type epitaxy, and collecting holes instead of electrons. Results show a typical trend for the shape of dark current and RTS degradation in CMOS image sensors (CISs) with the exception that the measured generation rates seem two times smaller than typical literature values in irradiated silicon. Different hypotheses on the origin of this discrepancy are explored.

This paper revisits the existing Clustering Probabilistic Binomial Reliability (CPBR) approximate analytical model based on circuit partitioning and signal transfer matrices. It demonstrates the model's relevance in assessing the correctness rate of logic gate netlists, in accordance with the ISO26262 road safety standard. The paper also highlights the model's applicability to typical industrial circuit netlists. While prior work established the CPBR model's ability to efficiently propagate signal error rates to circuit outputs with reasonable accuracy, no prior work has comprehensively compared its correctness rates to those of its reference Probabilistic Binomial Reliability (PBR) model. The novel CPBR implementation used in this paper enables, for the first time, a detailed accuracy comparison between the partitioning model and its reference across multiple circuits of the ISCAS’85 benchmark suite. Additionally, we provide an in-depth analysis of how this approximate method impacts the Automotive Safety Integrity Level (ASIL) for these circuits, identifying the optimal ASIL target for its application. Finally, we showcase the practical relevance of our approach by successfully applying it to the complex peripheral netlists of an industrial test-chip embedding a RISC-V core, demonstrating both its scalability and effectiveness in real-world scenarios.

This paper studies the fault propagation and the correctness rate calculation of combinatorial circuits. We rely on circuit partitioning and on a probabilistic approach close to a binomial distribution, assuming some simultaneous faults have a certain probability to occur in the circuit’s gates. We extend the results of our Clusterized Probabilistic Binomial Reliability model (CPBR), in which we obtained the results for several combinatorial multiplier designs, as seen in our previous publication. We now target non-arithmetic combinatorial netlists and, among them, a few circuits with flip-flop instances. We use the graph representation of the combinatorial netlists and we generalize our approach with a generic algorithm for CPBR. To develop this algorithm, we use some existing work on multilevel acyclic hypergraph partitioning, that we adapt to acyclic directed graphs. Furthermore, we address the problem of calculating correctness rates of circuits in cases where sequential flip-flops induce cycles in the graph. Our experiments show that our approach is capable of analysing the error and the correctness rates of significant non-arithmetic circuits, with an automatized and generic tool.

Gamma and X-ray irradiation results are reportedon several variants of deep-trench photogate research anddevelopment pixels from STMicroelectronics. Dark currentperformances are compared for electron and hole-collectingpixels (n, p-type) of 2 and 1 mu m pitch. Total ionizing dose(TID) results on 2 mu m p-type photogates are generally consistentwith previous studies, showing state-of-the-art radiation toleranceat 70 kGy (Si); 1 mu m n-type pixels are found to quicklydegrade under radiation, in line with expectations; 1 mu m p-typephotogates exhibit very promising radiation hardness, improvingon the 2 mu m p-type results by more than two orders of magnitude,with a dark current below 50 h(+)/s after 40 kGy gamma rays or64 kGy (Si) X-rays

The relentless pace of transistor miniaturization has enabled developers to continuously increase chip complexity since the beginning of the information age. However, as transistors get smaller and chips become larger, the cost of manufacturing ICs becomes increasingly prohibitive. As Moore’s Law is coming to an end, industry and academia have been exploring new paradigms to keep up with the ever-increasing demand for performance and functionality while dealing with the constraints of power consumption, area, and yield constraints. In this context, 3DICs are considered the future of the IC industry as they enable designers to fulfill both the “More Moore" and the “More than Moore" paradigm. A key feature of the 3DIC is that it can be manufactured by assembling multiple chiplets. Chiplets are single-purpose dies that must be assembled with other chiplets to form a complete system. Researchers and industry leaders believe that a chiplet market will form and that products with off-the-shelf chiplets will emerge. This scenario offers many economic opportunities. However, it also raises concerns regarding the security and trust (S&T) of chiplet-based designs. Malicious chiplets, Hardware trojans, and chiplet intellectual property theft are threats that must be addressed as the industry moves towards the “chiplet age". In this survey, we introduce the different types of 3DICs and their production chain.We then define the threats that threaten the different steps of the 3DIC manufacturing process. Finally, we present and discuss the state of the art in hardware S&T techniques for chiplet-based 3DICs.

As digital systems are continuously becoming more complex, new methods are required to ensure their resilience. Research and industry are working together to develop automated formal methods, and, recently, great progress has been made to overcome this challenge. This work describes a general procedure to quantitatively determine, by Model Checking, the resilience level of a digital block whose flip-flops are perturbed by bit-flips. The flow relies on the formal proof, and provides a rich variety of results with much improved performance and accuracy (boost of ~ 300x and ~ 30x in the two test cases). The resilience metric is the number of distinct counterexamples provided by the formal engine, for each fault target. Failure traces are differentiated in two ways, showing on the test cases the great enhancement over simulation.