A complete study of BaTi0.98Sn0.02O3 (BTS) thin films deposited on sapphire substrates by a sol-gel technique with physical and microwave dielectric properties up to 67 GHz is presented. A method derived from the techniques applied to silicon transistors and called de-embedding OPEN-SHORT is used for the extraction of interdigital capacitor features. The measurements allowing the calculations of tunability and loss tangent versus frequency are given from 500 MHz up to 67 GHz and bias points ranging from −20 to +20 V. Our results confirm that the BTS material is a very good candidate for microwave applications.

Self-aligned 0.55×3.5 μm 2 emitter InP/GaAsSb/InP double heterojunction bipolar transistors demonstrating an f t of 310 GHz and an f max of 480 GHz are reported. Common-emitter current gain of 24, together with a breakdown voltage of 4.6 V, is measured. The devices were fabricated with a triple-mesa process and easily fabricated with a new base isolation μ-airbridge design which, moreover, significantly reduced the base-collector capacitance C BC .

Microwave noise performance of state-of-the-art AIN/GaN high-electron-mobility transistors (HEMTs) grown on 100-mm Si substrate has been investigated. DC and RF measurements show the outstanding potential of this structure for high power millimeter-wave (mmW) applications. A maximum output current density of about 2 A/mm, together with a low gate leakage current, and a record GaN-on-Si extrinsic transconductance above 600 mS/mm are demonstrated. The current gain cutoff frequency f T and the maximum oscillation frequency f max were 85 and 103 GHz, respectively, with a 0.16-μm gate length. At V DS = 4 V, the device exhibits a minimum noise figure (NF min ) of 1 dB (1.8 dB) with an associated gain (G A ) of 12 dB (10 dB) at 10 GHz (18 GHz) favorably comparable to the best reported GaN-on-Si HEMTs. These results show that AIN/GaN HEMTs grown on silicon substrate are promising for the integration of cost effective, low noise, and high power mmW amplifiers.

The development of applications in millimeter wave range (mmW) during the last decade is strongly related to continuous progress of Si Technology, which kept on evolving through aggressive transistor gate length down-scaling. In this context, this paper aims to present DC, small signal and noise performance up mmW range of recently developed 45-nm bulk CMOS Technology. For this purpose, S parameters were measured up to 67 GHz, a high frequency (HF) noise model was extracted in 6-40 GHz frequency range, and its accuracy verified through a comparison with the noise figure measured in W band with a 50 Ω impedance set at the transistor. The technology offers fT, fMAX respectively of 200 and 300 GHz in line with up-to-date published results for a 45 nm CMOS Technology. At the meantime, a minimum noise figure of 4.5 dB at 94 GHz is demonstrated (verified through W band noise measurements).

AlN/GaN high-electron-mobility transistors (HEMTs) capped with an in-situ grown SiN have been successfully developed on 100 mm Si substrates. A unique combination of maximum output current density exceeding 2 A/mm and a record extrinsic transconductance above 600 mS/mm has been reached, which is well beyond the highest reported values of any GaN-on-Si HEMTs. The current gain extrinsic cutoff frequency fT and the maximum oscillation frequency fmax were 85 and 103 GHz with 0.16-µm gate length, respectively, resulting in a high fT·Lg product that promises low-cost, high performance millimeter wave electronics.

In this paper, the design and use of an in situ tuner (IST) aiming On-Wafer multi-impedance method are presented. The conventional method using Off-Wafer tuner is limited by the frequency range and has high losses between this external tuner and the device under test (DUT). Here, the IST is placed near the DUT to achieve higher |Γ| and to cancel losses between the impedance generator and the device. The architecture of the tuner is based on variable lumped R and C elements fulfilled with cold-field-effect transistor and varactors controlled through biasing and associated to coplanar transmission line for phase shifting. Detailed and dedicated noise de-embedding technique is described to extract the four noise (NFmin, Rn, Γopt) parameters of 65-nm metal-oxide-semiconductor field-effect silicon transistors through the use of this in situ multi-impedance method. The 75-110 GHz noise test bench using cold-noise source method and the noise measurement are described showing transistor capabilities at MMW.

In this paper, the best trade-off between low power consumption and low noise performance of a commercial bipolar transistor is investigated. In a first step, SiGe HBTs featuring various geometries are benchmarked, focusing on DC characteristics (Gummel plot); this allows the selection of the best device to be measured in microwave range. On this transistor, several figure-of-merits (FoMs) such as cut-off frequencies, minimum noise figure, and available gain, are extracted for the entire DC I(V) characteristic. With the help of iso-curves, our study allows to select optimized biasing range, useful for designers to design Low Noise Amplifiers (LNAs) featuring both low power and low noise performance.

Today, measurement of 65nm CMOS [1] and 130nm-based SiGe HBTs [2] technologies demonstrate both fT (current gain cut-off frequency) and fmax (maximum oscillation frequency) higher than 200 GHz, which are clearly comparable to advanced commercially available 100nm III–V HEMT. This increase allows new millimeter wave (MMW) applications on silicon. One of the success keys is then the passive integration. In this paper, on-chip coplanar waveguides (CPWs), which have been achieved in STMicroelectronics advanced nanometric RF CMOS High Resistivity (HR) SOI (ρ> 1kΩ·cm) process, and characterized up to 325GHz are reported. Moreover, for the first time passive circuits working @ 325GHz have been achieved on silicon and characterized demonstrating state-of-the-art performances and good agreement with electric simulations.

We present in this paper, a study of Dc, RF and Noise characteristics of an industrial metamorphic HEMT (High Electron Mobility Transistor) operating under low voltage at cryogenic temperature. The results at 300K are compared with the obtained results at cryogenic temperature. Temperature decrease makes device characteristics improve. This improvements allow to expect to develop a low power cryogenic electronic (LNA), featuring high frequency/noise performances below 100 mV DC biasing.

In this paper, we present a first full set of characteristics (dc, f T , f max , and noise) of InAs/AlSb high-electron mobility transistors (HEMTs) operating under cryogenic temperature and low-power conditions. Those results are systematically compared and deeply analyzed at room temperature and 77 K. The characteristics improvement achieved at 77 K open up the possibility to develop ultralow-power cryogenic electronics (low-noise amplifier), featuring excellent high-frequency/noise performances below 100-mV dc biasing.

This letter presents high frequency noise measurements carried out for MOSFETs in W-band (75-110 GHz). Because the 50 ¿ noise figure of 65 nm node MOSFETs is higher than 10 dB in W-band, pre-matched structures covering the entire band have been developed to reduce the noise figure and to increase the gain. Then, in order to validate the 2 temperatures noise model in W-band, only F50 measurements of pre-matched structures are necessary.

Measurement and modeling procedures to accurately extract a small-signal equivalent circuit of advanced MOSFETs up to 220 GHz are proposed. The methodology carried out goes from the vector network analyzer calibration to the simulation results using complex deembedding. Good comparisons between the measurement and the simulation data obtained using this procedure are shown up to 220 GHz.

This paper focuses on small signal and noise performances of Si/SiGe:C heterojunction bipolar transistors (HBT) under cryogenic temperatures. Two different technologies featuring state-of-the-art cutoff frequencies respectively for f T and f MAX are investigated. State-of-the-art minimum noise figures are reported both at room and cryogenic temperatures. A T small signal equivalent model to which is added a noise model has been extracted and is used to discuss the improvement of HBT performances at cryogenic temperatures.

In this paper, a measurement procedure with S parameters and Noise modelling for advanced, MOSFET technology is presented. The complete methodology is described from the VNA (Vector Network Analyser) calibration to the simulation results using a complex de-embedding procedure. A noise measurement bench in W band (75-110 GHz) has been developed using the well known F50 method. The comparison between measurements and model simulation shows good agreement up to 110 GHz. Such methodology leads to a robust MOSFET model designated for millimetre wave integrated circuit.