To enable continued BEOL scaling below 20 nm, Ru Direct Metal Etch (DME) integration has been proposed as an alternative to Cu damascene due to its lower resistivity. However, at these extremely aggressive pitches, the demands on lithography and patterning yield become increasingly critical. In this work, we demonstrate a simplified singleexposure 0.55 NA EUV dark-field patterning approach using metal-oxide dry photo resist (MOR) and dry development for Ru DME. Compared to multi-patterning schemes, the proposed flow eliminates pitch walk and reduces hard-mask complexity. Electrical yield is evaluated using large-area serpentine and fork structures for sensitive detection of line breaks and bridges. Under optimized conditions, dies show no electrically detectable line breaks or bridges for 20 nm pitch structures. The aggregate evaluated line length exceeds 1 m per die, and preliminary results indicate feasibility at 18 nm pitch. These results establish a viable path toward HVM (high-volume manufacturing) of sub-20 nm Ru DME interconnects.

We demonstrate for the first time a two metal level Ru interconnect using fully self-aligned vias (FSAV) landing on 16 nm metal pitch (MP). M-x lines are patterned using EUV-SADP and direct metal etch of Ru in a spacer is dielectric (SID) integration scheme. With a critical dimension (CD) of 8 nm Mx lines measure an average of 670 Omega/mu m with a yield of >95% across a 300 mm wafer and average resistivity of 15.5 mu Omega.cm extracted from TCR measurements. FSAV via performance is competitive with a measured resistance value of 14 Omega for >95% yield across the full wafer. This effort is a crucial step towards the tight pitch requirements of standard cell scaling and CFET implementation.

Constantly evolving with several revolutionary technologies, High NA EUV Lithography is at the forefront of the semiconductor industry. It enables the patterning of sub-10nm features, dramatically boosting transistor density and chip performance. This technology is essential for propelling Moore's Law into the future. Early access to TWINSCAN EXE:5000 High NA EUV scanner, a state-of-the-art facility in the joint ASML-imec HNA EUV Lithography Lab, has enabled the exploration of leading-edge random via use cases. This access facilitates testing HNA EUV use cases, refining manufacturing processes, and accelerating innovation. In this paper, we share the result of imec's first HNA EUV reticle. Key highlights of this work include demonstrating defect-free random vias with a 29.7nm center-to-center (C2C) distance, corresponding to underlayer metal grids of 22nm x 20nm pitch. We show excellent pattern fidelity showcasing LCDU similar to 1.5nm, validating the process for even smaller via dimensions at 0.55 NA.

This study investigates the overlay performance of a 2-level Ru semi-damascene integration using a Spacer-is-Dielectric (SID) SADP strategy to create 18 nm metal pitch Ru metal lines combined with fully self-aligned vias (FSAV). Furthermore, the impact of via overlay on FSAV electrical performance was experimentally assessed. Results show that <= 3 nm lot M(x)block-to-M-x overlay residuals can be achieved using an SID-SADP approach with TiN as hard mask. Moreover, an >80% kelvin via yield could be obtained for a via y-overlay range of 10 nm and via x-overlay range of 11 nm, highlighting the FSAV process's robustness for future interconnect scaling.

Ru post dry-etch surfaces are exposed to UV irradiation and subsequent wet cleaning, to remove post etch residues. The nature of these residues, their removal efficiency and mechanisms are investigated. The post etch surface consists of native oxides of Ru and Ti along with Cl-impurities. Both UV and UV + wet cleaning processes are found to reduce the native oxide and Cl-residues, increase the hydrophilicity of the surface and improve the residue removal efficiency by improving the wetting of the small trenches (9 nm CD) in the patterned structures (18 nm metal pitch). Leakage measurements show an improvement in the leakage yield from similar to 30% to similar to 50% at a current of 1x10(-11) A.

This work presents the integration of MP16/18 in a spacer-is-dielectric SADP Ru semi-damascene integration scheme through a novel SiN-based core and gap hard mask integration flow. This approach lowers the cost of single metal layer processing by 60% compared to a metal-based core approach. It also enables more than 80% yield on MP18 lines and the first ever reported electrical measurements of MP16 line structures in literature achieving 40% yield across a 300mm wafer, with an average resistance of 524 Omega/mu m (MP18) and 656 Omega/mu m (MP16). MP18 leakage structures show a low line-to-line leakage at 1.2V achieving 80% yield with a breakdown voltage in the range of 8-11V.

This work reports variable metal width Ru semi-damascene bottom metal line integration at metal pitch (MP)=18-26 nm, for the first time at high-aspect ratios of 4 and 6. It is also the first report on routing of such lines to a top semi-damascene metal level using a fully self-aligned via (FSAV). Average core-gap line resistance (R) at MP=18 nm is similar to 240 Omega/mu m at AR6. Line-line leakage yields of 50% and 30% at AR4 and AR6, respectively, is achieved at MP=18 nm which exceed 90% and 70% at MP=20 nm. MP=18 nm, AR4 line-line TDDB at 100 degrees C show an extrapolated failure time of >10y. Ru FSAV fabricated on AR4, MP=18 nm Ru line has a kelvin resistance of similar to 20 Omega at via bottom CD similar to 9.4 nm and via height similar to 8.4 nm. Electromigration (EM) on single vias show robust Ru-Ru interface with no failures post 135h of EM stress at similar to 10 MA/cm(2) and 330 degrees C.

In order to achieve tight, 8 to 12 nm cell boundaries, Ru direct metal etch can be used to split a larger via into two opposite facing smaller vias and create a tight metal line tip-to-tip (T2T) at the cell boundary. This is obtained by self-aligning the Ru direct metal etch to the tightest metal layer above. This technique of splitting a via and creating a T2T with zero line extension is promising for cell boundary definition of complementary FET. In this work, we will discuss lithography overlay and via CD process window definition to achieve the improved morphological and electrical results. For 8 nm T2T, we have obtained a 55% leakage current yield. Additionally, for 10 and 12 nm T2T, a leakage current yield of above 90% was achieved.

This work presents a novel Spacer-is-Dielectric (SID) SADP Ru semi-damascene integration scheme by using metal-based core and gap hard masks. More than 70% yield in tested line resistance and line-to-line leakage, especially in MP18 structures, confirm the flow feasibility. The tested MP18 structures show a median line resistance of, low line-to-line leakage at 1V, and breakdown voltages in the range of 12-14V.

Airgap integration in 18 to 26 nm metal pitch (MP) two-metal level semi-damascene interconnects with fully self-aligned vias (FSAV) on 300 mm wafers is reported. The first metal layer (Mx) is patterned using EUV-SADP with subsequent direct metal etch of the Ru film. Airgap is integrated at a targeted height of 4-6 nm below the top metal lines allowing for FSAV compatibility. 80% of kelvin vias landing on Mx at MP18 meet the < 50 ohm resistance target specification and 40% of them meet the via-to-line leakage target of <100 pA. The airgap line-to-line capacitance is found to be 40% lower compared to the dielectric gap fill reference.

To accommodate the A10 node a further scaling down of the metal line pitch towards MP16 is envisaged. As high NA will be close to its practical limit for direct P16 L/S patterning, low NA self-aligned double patterning (SADP) from P32 towards P16 was explored. First, lithography conditions such as source and stack were optimized by investigating process windows, uLER/uLWR and ebeam defectivity throughout the P32 core patterning process. Then, with the optimized lithography conditions a CDU wafer was subjected to SADP patterning.

In this paper we will present initial results for logic and memory features imaged with the TWINSCAN EXE:5000 at the ASML-imec high NA lab after successful etch pattern transfer. For logic applications random logic metal designs (consisting of tight pitches and aggressive tip-to-tips) and corresponding via structures have been characterized for A14 and A10 nodes. As well, bidirectional designs enabled by high NA will be described. For memory applications, results from BLP/SNLP layer for D1d and D0a nodes will be presented.

This study highlights the effectiveness of a novel two-metal-level semi-damascene integration approach using fully self-aligned pillar-vias (FSAV) for interconnects ranging from 18 to 26 nm metal pitch. We employ EUV-SADP-SIM patterning scheme and direct metal etch of Ru to demonstrate the proof of concept on 300 mm wafers. This integration gives lower via resistance than the previously reported schemes and promises lower capacitance. Furthermore, it significantly widens the via litho and etch process window, making it more attractive for advanced semiconductor manufacturing.

A novel metal stack scheme with a sub-nm, sandwiched TiN or W layer, a so-called defect mitigation layer (DML) between Ru is proposed and found to be less prone to lateral attack and line-break formation during direct-metal-etch (DME) of Ru semi-damascene (semi-D) lines compared to those without DML. With increasing thickness (t k ) of TiN-DML, we achieve up to 5x lower defect density and resistance (R) yield >99%, <5% 1 σ of R on AR~4-6, CD~6-11 nm, metal pitch (MP)=18-26 nm lines. The improvement is higher on AR~6 lines than AR~4 which makes DML a promising approach to enable AR≥6 semi-D interconnects. No R penalty is found with TiN-DML for the investigated line lengths> 10 μm. Thermal shock reliability test shows good quality of HAR Ru line interfaces with TiN-DML.

Microchip downscaling has been one of the main drivers on the semiconductor industry to enable faster, more efficient, and compact microchips, greatly broadening their range of applications, like the Internet of Things, smart mobility, artificial intelligence and 5G, among others. Aside from transistor scaling, the Back End of Line (BEOL) interconnection network, which transfers power and signals from and into the transistors, must also be scaled down consequently. The scaling requirements have surpassed the maximum resolution achievable by any lithographic technique by solely relying on direct printing. In the case of low numerical aperture, Extreme UV (low NA EUV), the most advanced, commercially available lithography technology, printing line/space structures below pitch 30 nm (P30) is extremely challenging [1]. However, 3nm and newer nodes require BEOL line space structures with P26 nm or narrower, in particular for the M2 layer. It is here where multipatterning techniques come into play. Self-Aligned multipatterning techniques allow to divide by a factor of two (double patterning, SADP), four (quadruple patterning, SAQP) or even eight (octuple patterning, SAOP) the pitch printed at lithography level, easing the lithography requirements [2]. However, with multipatterning, there comes a risk that not all interconnect lines would be patterned with equal dimensions, which would introduce resistance and capacitance variations across lines that theoretically should be equivalent. Hence, all multipatterning techniques require a precise control of each of the fabrication steps to guarantee that all lines and spaces present the same dimensions, i.e., a balanced patterning with no pitch walking. The target of our work is to find the fabrication parameters that lead to the lowest pitch walking, roughness and defectivity conditions on EUV SADP patterning (eSADP) at P21 nm structures with 10.5 nm metal line Critical Dimension (CD). Thus, we carried out a set of experiments where the printed lithography line CD and the spacer thickness values are swept on 300 mm silicon wafers. Then, we analyze the patterning performance at different stages of fabrication to see the evolution of line and space CDs, roughness and defectivity values to determine the best candidate for P21 nm eSADP patterning.