Silicon spin qubits are among the most promising candidates for large scale quantum computers, due to their excellent coherence and compatibility with CMOS technology for upscaling. Advanced industrial CMOS process flows allow wafer-scale uniformity and high device yield, but off the shelf transistor processes cannot be directly transferred to qubit structures due to the different designs and operation conditions. To therefore leverage the know-how of the micro-electronics industry, we customize a 300mm wafer fabrication line for silicon MOS qubit integration. With careful optimization and engineering of the MOS gate stack, we report stable and uniform quantum dot operation at the Si/SiOx interface at milli-Kelvin temperature. We extract the charge noise in different devices and under various operation conditions, demonstrating a record-low average noise level of 0.61 μeV/√(Hz) at 1 Hz and even below 0.1 μeV/√(Hz) for some devices and operating conditions. By statistical analysis of the charge noise with different operation and device parameters, we show that the noise source can indeed be well described by a two-level fluctuator model. This reproducible low noise level, in combination with uniform operation of our quantum dots, marks CMOS manufactured MOS spin qubits as a mature and highly scalable platform for high fidelity qubits.

The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers1,2. As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical3. Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal-oxide-semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 mu s. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing4. Moreover, it offers the potential for further upscaling through three-dimensional integration5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors. Superconducting transmon qubits have been fabricated in a 300 mm complementary metal-oxide-semiconductor (CMOS) pilot line using industrial fabrication methods, achieving relaxation and coherence times exceeding 100 mu s.

We report a comprehensive 300 mm industrial silicon spin qubit integration process for large scale quantum processors. The process was designed to be modular to enable the identification and optimization of the key elements for qubit performance and upscaling. The devices can be fabricated on Si or SiGe substrates with PolySi or TiN metal for the gate electrodes. The modular approach is extended to qubit control structures enabling both ESR antennas and EDSR micromagnets. Various quantum dots and sensors, on both platforms, are measured in a dilution refrigerator at temperatures $\sim 10$ mK. Electrical characterization of the quantum dots demonstrates low disorder and excellent charge stability down to the last electron. Finally, we demonstrate coherent spin manipulation using an ESR antenna. These low-disorder, high performance qubits mark CMOS manufactured spin qubits as a mature platform for large scale quantum computing.