The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers1,2. As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical3. Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal-oxide-semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 mu s. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing4. Moreover, it offers the potential for further upscaling through three-dimensional integration5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors. Superconducting transmon qubits have been fabricated in a 300 mm complementary metal-oxide-semiconductor (CMOS) pilot line using industrial fabrication methods, achieving relaxation and coherence times exceeding 100 mu s.

While the semiconductor industry has reached the high-volume manufacturing of the 7 nm technology node (N7), patterning processes for future technology nodes N5, N3 and even below, are being investigated and developed by research centers. To achieve the critical dimensions of gratings for these future technology nodes, we require multipatterning approaches, such as self-aligned double/quadruple/octuple patterning (SADP/SAQP/SAOP) and multiple litho-etch (LE) patterning, in combination with 193i lithography and even EUV lithography. These gratings need to be subsequently cut or blocked, which is typically done by one or more block masks. As the edge placement error (EPE) budget drastically decreases with decreasing critical dimensions, the standard LE block patterning scheme is not sufficient anymore. To relax the EPE budget, dedicated scaling boosters are required such as the self-aligned block scheme, which defines blocks in trenches, selectively to the neighboring trenches. In this work we explore the different multipatterning options for lines and blocks at pitches below 20 nm. As such, we will demonstrate and compare three different patterning options to enable 16 nm pitch gratings: 193i-based SAOP, EUV-based SADP and EUV-based SAQP. Finally, we will also elaborate on a self-aligned patterning scheme which does not define lines and blocks sequentially anymore but integrates them in a mixed mode. This patterning approach (SALELE) makes use of two LE masks and two self-aligned block masks. We will present its development status at relaxed pitch (28 nm) and discuss its advantages for future technology nodes.

This paper discusses the approach for patterning 15nm Half Pitch (HP) structures using EUV lithography combined with Self-Aligned Double Patterning (SADP). A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an alpha-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of LWR, LER and CDU, targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER and CDU at 15nm HP are demonstrated.

Defectivity has been one of the largest unknowns in immersion lithography. It is critical to understand if there are any immersion specific defect modes, and if so, what their underlying mechanisms are. Through this understanding, any identified defect modes can be reduced or eliminated to help advance immersion lithography to high yield manufacturing. Since February 2005, an ASML XT: 1250Di immersion scanner has been operational at IMEC. A joint program was established to understand immersion defectivity by bringing together expertise from IMEC, ASML, resist vendors, IC manufactures, TEL, and KLA-Tencor. This paper will cover the results from these efforts.The new immersion specific defect modes that will be discussed are air bubbles in the immersion fluid, water marks, wafer edge film peeling, and particle transport. As part of the effort to understand the parameters that drive these defects, IMEC has also developed novel techniques for characterizing resist leaching and water uptake. The findings of our investigations into each immersion specific defect mechanism and their influencing factors will be given in this paper, and an attempt will be made to provide recommendations for a process space to operate in to limit these defects.

The immersion-specific watermark defect is discussed in its formation mechanism and in the influence of materials and exposure process. The non-topcoat approach was the basis of the work, where the properties of resist surface itself played the key role. Water droplets left on the resist surface were considered to induce the watermark defect in two possible ways; (1) the droplet is carried over to PEB process and impact the resist properties under the heat, (2) the droplet already evaporates before the PEB leaving some residue on the surface. A notable reduction in the resist dissolution rate was observed in the former case, which could be due to either physical or chemical change in the resist materials triggered by the water, and thereby would result in an unavoidable patterning failure. Therefore it is essential not to leave any water droplets on the surface in preventing the watermark formation. A very much hydrophobic materials design was proven effective in achieving this. The watermark formation was correlated to the scanning speed of immersion showerhead and the defectivity was evaluated in this perspective. The receding contact angle of the resist surface was found to well correlate to the "allowable" scanning speed, and was concluded that the higher was the better. A resist material was newly designed by using a hydrophobic polymer on this basis and the resist demonstrated a promising results not only in the watermark defectivity but also in lithographic performance.

Since the moment immersion lithography appeared in the roadmaps of IC manufacturers, the question whether to use top coats has become one of the important topics for discussions.The top coats used in immersion lithography have proved to serve as good protectors from leaching of the resist components (PAGs, bases) into the water. However their application complicates the process and may lead to two side effects. First, top coats can affect the process window and resist profile depending on the material's refractive index, thickness, acidity, chemical interaction with the resist and the soaking time. Second, the top coat application may increase the total amount of defects on the wafer.Having an immersion resist which could work without the top coat would be a preferable solution. Still, it is quite challenging to make such a resist as direct water/resist interaction may also result in process window changes, CD variations, generation of additional defects.We have performed a systematic evaluation of a large number of immersion resist and top coat combinations, using the ASML XT: 1250Di scanner at IMEC. The samples for the experiments were provided by all the leading resist and top coat suppliers. Particular attention was paid to how the resist and top coat materials from different vendors interacted with each other. Among the factors which could influence the total amount of defects or CD variations on the wafer were: the material's dynamic contact angle and its interaction with the scanner stage speed, top coat thickness and intermixing layer formation, water uptake and leaching. We have examined the importance of all mentioned factors, using such analytical techniques as Resist Development Analyser (RDA), Quartz Crystal Microbalance (QCM), Mass Spectroscopy (MS) and scatterometry. We have also evaluated the influence of the pre- and pos- exposure rinse processes on the defectivity.In this paper we will present the data on imaging and defectivity performance of the resists with and without the use of top coats. So far we can conclude that top coat/resist approach used in immersion lithography needs some more improvements (i.e. process, materials properties) in order to be implemented in high volume manufacturing.

Lithographers are preparing their processes for the 130nm node. About one year ago, first generation full field ArF step and scan systems have been introduced in a number of fabs. These systems have lenses with numerical apertures in the order of 0.6. At the same time, 0.7 NA KrF step and scan systems have been introduced as well. Also last year, KrF resists were shown to be much more mature than ArF resists.