Photon Emission (PE) from Integrated Circuits (IC) is an emerging non-invasive side channel that poses a serious security risk to modern System-on-Chips (SoCs). These emissions, generated during transistor switching, are determined by circuit operations and can be exploited in Side-Channel Analysis (SCA). Furthermore, physical design choices, such as standard cell placement and routing, affect how these emissions propagate and are detected. This makes it crucial to assess and mitigate such risks during the design phase. This paper presents a novel photonic side-channel analysis framework that integrates directly into the physical design flow. The framework enables designers to assess security vulnerabilities in digital ASIC designs by generating both time-resolved and accumulated PE maps at the standard-cell gate level. These PE maps can be applied to various side-channel analysis methods to identify vulnerable regions in the circuit. We demonstrate the framework by applying it to a 40nm 128-bit Advanced Encryption Standard (AES) core, where we employ localized Correlation PE Attacks (CPEA) on simulated time-resolved PE maps. This approach pinpoints regions with high side-channel leakage. The results showcase the framework's effectiveness in providing early detection and allow designers to enhance the overall security of the design against PE-related vulnerabilities. To validate our simulation framework, we compared the simulated accumulated PE maps with real-world measurements from a 40nm AES test chip. The close alignment between simulated and measured data confirms the accuracy of our simulator in predicting photon emission behavior across the chip.

Nonvolatile memory based on conductive bridge random access memory or memristors is widely considered as a candidate for next generation memory devices for artificial intelligence. Two-dimensional (2D) materials have unique layered structures contributing to the distinct electrical and mechanical properties, which provides the immense potential in memory devices. Chemical vapor deposition (CVD) growth of 2D materials allows for synthesis of large-area films, making it more feasible than small exfoliated flakes for memristor applications. Here, we report CVD-grown MoSe2 based memory devices. The device utilized the metal–insulator–metal structure, where a 6 nm thick multilayer MoSe2 film was sandwiched in between top and bottom electrodes. With a lower compliance current, the device shows a volatile switching behavior due to the thermodynamically unstable filament formation. The transition from volatile to non-volatile switching can be achieved by higher compliance current >900μA at room temperature. We also study the conduction mechanism by analyzing the non-volatile DC sweeps from the SET process. In addition, the activation energy of Ag is estimated by the temperature dependent retention ability study. Finally, the switching performance for 50 ns pulses with >500 cycles endurance demonstrates the potential in RF and computing applications.

Tungsten diselenide, WSe2, is attractive as a channel material for p-channel metal–oxide–semiconductor field effect transistors (PMOSFETs) using transition metal dichalcogenide (TMD) nanosheets for ultimate CMOS scaling. For practical applications, it is necessary to demonstrate good quality devices on as-grown, large-area chemical vapor deposition (CVD) grown TMD films, rather than on small, exfoliated flakes from bulk crystals, and without requiring transfers to secondary substrates. This article reports on the growth optimization of large-area WSe2 and efforts to achieve higher hole conduction, which is more challenging than electron conduction since most TMDs tend to be n-type due to defects. Achieving low contact resistance and high drive currents is vital, but the intrinsic defects within the grown material dominate the carrier mobilities and effectively make TMDs more n-type due to chalcogen vacancies in devices fabricated at high temperatures. We have, therefore, developed salt-assisted growth strategies at different growth temperatures using atmospheric pressure CVD (APCVD). Furthermore, we identified optimal APCVD growth and PMOSFET fabrication recipes to achieve high hole conduction. With growth and fabrication optimization, we can achieve drive currents of 10 μA/μm in back-gated PMOSFETs at Vd = −2 V in as-grown WSe2, akin to their exfoliation-based counterparts. We also have seen evidence of both hole and electron ambipolar conduction even with high work function source/drain contact metals, signifying that contact engineering will be vital to suppress the electron branch and improve hole conduction.

Low-temperature large-area growth of two-dimensional (2D) transition-metal dichalcogenides (TMDs) is critical for their integration with silicon chips. Especially, if the growth temperatures can be lowered below the back-end-of-line (BEOL) processing temperatures, the Si transistors can interface with 2D devices (in the back end) to enable high-density heterogeneous circuits. Such configurations are particularly useful for neuromorphic computing applications where a dense network of neurons interacts to compute the output. In this work, we present low-temperature synthesis (400 degrees C) of 2D tungsten diselenide (WSe2) via the selenization of the W film under ultrahigh vacuum (UHV) conditions. This simple yet effective process yields large-area, homogeneous films of 2D TMDs, as confirmed by several characterization techniques, including reflection high-energy electron diffraction, atomic force microscopy, transmission electron microscopy, and different spectroscopy methods. Memristors fabricated using the grown WSe2 film are leveraged to realize a novel compact neuron circuit that can be reconfigured to enable homeostasis.

Diffusive memristors made with conductive metal bridge random access memories (RAMs) have been studied for low power consumption and linearity of integrate/fire characteristics of artificial neurons by using a defective graphene interlayer. Utilizing this approach, a volatile artificial neuron incorporating Ag demonstrates sustained low-power characteristics inherent to Ag-based devices, accompanied by linearity in spike occurrence through precise control of on/off-current ratio and conductive filament dissolution time. This approach enables the precise tuning of the neuron's behavior and offers potential applications in neuromorphic computing and artificial intelligence.

Recently, nonvolatile resistive switching memory effects have been actively studied in two-dimensional (2D) transition metal dichalcogenides and boron nitrides to advance future memory and neuromorphic computing applications. Here, we report on radiofrequency (RF) switches utilizing hexagonal boron nitride (h-BN) memristors that afford operation in the millimeter-wave (mmWave) range. Notably, silver (Ag) electrodes to h-BN offer outstanding nonvolatile bipolar resistive switching characteristics with a high ON/OFF switching ratio of 1011 and low switching voltage below 0.34 V. In addition, the switch exhibits a low insertion loss of 0.50 dB and high isolation of 23 dB across the D-band spectrum (110 to 170 GHz). Furthermore, the S21 insertion loss can be tuned through five orders of current compliance magnitude, which increases the application prospects for atomic switches. These results can enable the switch to become a key component for future reconfigurable wireless and 6G communication systems.

Threshold switches based on conductive metal bridge devices are useful as selectors to block sneak leakage paths in memristor arrays used in neuromorphic computing and emerging nonvolatile memory. We demonstrate that control of Ag-cation concentration in Al2O3 electrolyte and Ag filament size and density play an important role in the high on/off ratio and self-compliance of metal-ion-based volatile threshold switching devices. To control Ag-cation diffusion, we inserted an engineered defective graphene monolayer between the Ag electrode and the Al2O3 electrolyte. The Ag-cation migration and the Ag filament size and density are limited by the pores in the defective graphene monolayer. This leads to quantized conductance in the Ag filaments and self-compliance resulting from the formation and dissolution of the Ag conductive filament.

The conventional theory of superconductivity holds that Cooper pairs form due to electron–phonon coupling; however, this description may not be adequate to describe certain unconventional superconductors such as cuprates and iron chalcogenides. In these unconventional superconductors, it has been proposed that spin fluctuations may be responsible for the formation of Cooper pairs. In this study, we explore spin interactions in the transition metal, dichalcogenide niobium disulfide, induced through proximity effects by fabricating antiferromagnet/NbS2 heterostructures. We tested three different 2D antiferromagnetic materials, each with different spin textures: anganese phosphorus trisulfide, manganese phosphorus triselenide, and chromium trichloride. Our results showed a substantial reduction in the critical temperature in the case of NbS2/MnPSe3. We hypothesize that this could be due to spin fluctuations in MnPSe3 inducing proximity effects in NbS2.

Technology scaling gives rise to challenges in efficient power delivery for sub-5nm nodes. Buried Power Rail (BPR) interconnect technology is a promising solution for efficient monolithic power delivery. It provides power-performance-area (PPA) metric gains without actual dimensional scaling. With the introduction of any new technology, it is important to characterize it for potential security threats to critical blocks. This work evaluates the security robustness of BPR technology, providing insights on how the side-channel leakage changes with power delivery network (PDN) configuration, and comparing risks to critical private information. Choosing an open source 7nm FinFET as the baseline technology, three PDN variants are modelled by modifying the technology files. We design a crypto-IP (128-bit Advanced Encryption Standard) and extract their physical/electrical properties. Using custom simulators, the electromagnetic side channel attack vulnerability is analyzed and quantified. Our analysis reveals that BPRs tend to be more vulnerable when employed with backside metal routing, leaking side-channel information more strongly. The results suggest the need for robust pre-silicon design techniques and methodologies to mitigate the side channel attack vulnerabilities.

Buried power rails and back-side power grids are promising technology-scaling boosters for advanced CMOS technology nodes. System-level evaluation of these technologies shows tremendous promise from power-performance-area (PPA), IR drop, and dynamic voltage droop perspective. However, several process, device, and architectural challenges must be addressed to realize the full potential of this technology. This article reviews the advancements and challenges in successfully adopting buried power rail and back-side power grid technology.

Buried power rail (BPR) and back-side power delivery grid have been proposed as solutions to scaling challenges that arise beyond the 5-nm technology node, mainly to lower IR drop and further shrink area. This article demonstrates a holistic evaluation of this technology and its variants at the microprocessor level. This is carried out by taking an Arm Cortex-A53 design through the standard-VLSI physical design implementation flow on Imec’s iN6 node, equivalent to the industry 3-nm technology node, which features the buried power technology. The power, performance, area, on-chip IR drop, and off-chip voltage droop metrics are benchmarked, and implications on power gating are explored. An extensive Design-Technology-Co-Optimization (DTCO) study of the back-side power grid is presented to enhance the decoupling capacitance by sweeping associated technology parameters showcasing further optimization opportunities in manufacturing. The conclusions of this work highlight that the front-side (FS) power delivery network (PDN) with buried rails achieves a 25% lower on-chip IR drop and 17% lower off-chip voltage droop (power supply noise) resulting in 21% lower guard band voltage. On the other hand, the back-side power grid with BPRs achieves 85% lower on-chip IR drop and 30% off-chip voltage droop resulting in 60% lower guard band voltage. In addition, the impact of BPRs, and back-side power grids on power gated designs are evaluated.

Multilevel cell (MLC) Resistive Random Access Memory (RRAM) is an attractive technology option to realize ultra-high density, low-power memory arrays [1]. Traditional 1-transistor 1-resistor (1T1R) bitc ell suffers from adjacent state overlap due to the inherent RRAM variations which hinders the realization of MLC capability [2]. In this work, we evaluate an alternate 2-transistor 1-resistor (2T1R) gain-cell RRAM bitcell topology that has higher read-out dynamic range and exhibits higher process variation tolerance compared to the baseline 1T1R bitcell [3]. We perform a thorough statistical estimation and variability analysis for both single-level cell (SLC) and MLC operation. For SLC operation, 2T1R can tolerate up to 400,70 higher RRAM variations than 1T1R and up to 200% higher variations for an iso-read power comparison. For MLC operation, it is 20-30% more variation tolerant and can provide the same robustness at lower read power. The write power of both bitcells is almost identical due to similar write mechanisms.

Resistive switching in 2D materials such as hexagonal boron nitride (hBN) and Transition Metal Dichalcogenides (TMDs) have been demonstrated recently [1]–[3]. These memory devices with an ultra-thin switching layer have the potential to achieve low operating voltages, low variability and are also suitable for flexible electronic applications [4]. Here we report the first experimental observation of sub-nanosecond switching of 2D hBN based resistive random access memory (RRAM) devices. This is the fastest switching speed in 2D RRAMs, surpassing the previously reported 5ns switching [5]. Devices also exhibit consistent repeatable switching between high-low memory states with ultra-short pulses (pulse-width ~ 2.7ns).

The rapid growth in development of neural networks has necessitated the requirement of large capacity on-chip SRAM’s for Machine Learning accelerators. This has resulted in SRAM’s occupying significant portion of the die area. Furthermore, due to increased short channel effects in advanced CMOS technology nodes, the Vt of the transistors are increased to reduce the leakage power effectively. Vt increase results in direct increase in V MIN (minimum operating voltage) of the device. The conventional 6T SRAM with the use of RRAM(R) to store the bitcell storage node values and PTM(S) as a selector device (6T-2R-2S) can help in decoupling V MIN and Vt requirement with minimum area overhead. Functionalities of 6T-2R-2S bitcell are investigated to present a 2T-2R-2S mode and SRAM-RRAM hybrid mode of operation, further utilized in performing Compute in Memory(CIM). The above functionalities can be presented in a 8T2R bitcell, that makes use of transistor in place of PTM. 2T-2R-2S/2T-2R mode is a fully non-differential mode of operation, leveraging only the NVM portion of the bitcell. Furthermore, SRAM-RRAM hybrid mode is proposed making use of the SRAM read port transistors to perform read operation of the data stored on the RRAM, during standby mode. The architecture study of set-associative cache made of 6T-2R-2S array is also presented. The 2T-2R-2S/2T-2R mode coupled with SRAM-only mode can be efficiently used to perform CIM for dot product and XNOR computation with co-locating the weights and activations stored onto the same bitcell. System level study highlighting energy efficiency and speedup along with the proposed CIM architecture’s analysis on CIFAR-10 dataset is presented. Design sensitivity analysis with respect to PTM and RRAM parameters is discussed for both the bitcells.

We propose device and circuit assist techniques to lower the ferroelectric–metal field-effect transistor (FeMFET) write voltage while lowering the effect of depolarizing field. A bipolar threshold selector (TS) is connected between the intermediate node of a FeMFET and ${V}_{\text {SS}}$ , which provides a low-impedance bypass path by triggering an insulator to metallic transition during a write operation. This lowers the voltage drop across MOSFET and reduces the write voltage to ~1.7 V. For further reduction in write voltage, the MOSFET in the FeMFET is utilized as a circuit assist by repurposing it as a capacitive coupling device. It reduces the write voltage to ~1.4 V. During the read mode, TS is in insulating state and does not alter the capacitive voltage divider action. Read is followed by a data-dependent write-back stage to bring the polarization close to retention polarization. During the retention mode, TS acts as a weak bleeder resistor, reducing noise coupling and depolarizing field. TS parameter sensitivity for write voltage reduction along with row hammer effect of the proposed read- and write-back operation is also presented.

In this work, we demonstrate a compressed time-domain, pooling-aware convolution (COMPAC) convolutional neural network (CNN) engine for energy-efficient edge AI computing by performing multi-bit input and multi-bit weight multiply-and-accumulate (MAC) operations in the time domain. The multi-bit inputs are compactly represented as a single pulsewidth encoded input. This translates into reduced switching capacitance ( C DYN ), compared with the baseline digital implementation, and can enable low-power neural network computing in an edge device. COMPAC CNN engine employs a novel and an improved version of the memory delay line (MDL) supporting the time residue scaling to perform the signed accumulation of multi-bit input and multi-bit weight products in the time domain. The compressed time-domain (CTD) approach is proposed to improve the throughput in time encoding of the input activations. The simulation results of the proposed CTD approach on the AlexNet CNN over 1000 ImageNet images show that 14.71 and 7.15 input clock cycles are consumed to time-encode an 8-bit input activation in two different CTD modes, improving the throughput by 88.60% and 94.46%, respectively, compared with the conventional pulsewidth modulation-based time-domain encoding. Furthermore, a pooling-aware convolution (PAC) technique is proposed to reduce the number of redundant MAC computations for the convolution layers that are followed by the max-pooling layer. The simulation results on the AlexNet CNN over 1000 ImageNet images show up to 31.47% (21.79%) reduction in the number of non-zero input activations MACs with a top-five classification accuracy loss of 0.60% (0.90%) with an on-chip access overhead of 60.53% (8.03%) for the PAC modes 1 (2) respectively. Finally, energy-efficient data flow for optimal on-/off-chip memory accesses for the time-domain MAC computation is proposed. COMPAC data flow the results in 86.97% reduced on-chip accesses and 29.74% reduced off-chip accesses compared with the Eyeriss approach, at iso-bit precision. COMPAC CNN engine implemented in 65-nm CMOS test chip demonstrates an energy efficiency of 1.044 TOPS/W and the throughput of 0.1278 GOPS at 720 mV for the AlexNet. The top-five classification accuracy of 76.90% measured over 1000 ImageNet images and 77.15% by simulating over 50 000 ImageNet images is achieved. The simulation results comprehending MDL circuit non-idealities for the AlexNet over 50 000 ImageNet validation set images show a classification accuracy loss within 1% compared with the 8-bit fixed-point software implementation.

The threshold switching properties of the phase transition material (PTM) can be exploited to realize a heterogeneous static random access memory (SRAM) bitcell, which can obviate the need for assist techniques. This unique PTM-SRAM bitcell is designed by placing the PTM in series with the gate of pull-down nMOS transistors. The large insulating state resistance of the PTM device blocks the propagation of read voltage rise during a read operation and noise during retention operation, thereby enhancing read/retention stability. On the flip side, the write-time and write-ability are impacted, which can be improved by tuning the access transistor strength. Overall, the PTM-SRAM bitcell achieves active- $V_{\text {MIN}}$ equivalent to baseline SRAM $V_{\text {MIN}}$ aided by both read- and write-assist techniques. Furthermore, the read access time of the PTM-SRAM bitcell does not degrade with reducing read $V_{\text {MIN}}$ in contrast to other read-assist techniques. For an isoactive- $V_{\text {MIN}}$ of 0.52 V, the PTM-SRAM has 20% lower read access time, 35% lower read power, 16% higher write time, and 55% lower write power compared to the baseline SRAM aided by assist techniques. Also, the dynamic retention stability of the PTM-SRAM improves by $11.36\times $ compared to baseline SRAM. Detailed analysis highlighting the sensitivity of PTM parameters on PTM-SRAM performance metrics is also presented.

Solid-state electrolytes have attracted significant attention in rechargeable battery and solid-state device research due to the added benefits over the liquid electrolytic counterpart owing to their solid nature. Here, we demonstrated centimeter-scale growth of MoS 2 thin film, a promising two-dimensional (2D) material for transistor and energy storage, on Li-ion solid electrolyte substrate by sulfurization of Molybdenum thin film. The sulfurized film was characterized using a combination of spectroscopic and microscopic analyses, including optical microscopy, X-ray photoelectron spectroscopy, X-ray diffraction, and Raman spectroscopy. The film was further characterized by electrical probing to measure the film quality and underlying transport mechanism.

Operating CMOS circuits at cryogenic temperatures offers advantages of higher mobility, higher ON-current, and better subthreshold characteristics, which can be leveraged to realize high-performance CMOS circuits. However, an ultra-low-voltage operation is necessary to minimize the power consumption and to offset the cooling cost overheads. The MOSFET threshold voltages (Vt) increase at cryogenic temperatures making it challenging to achieve high performance while operating at very low voltage. Ultra-thin body and buried oxide silicon-on-insulator (UTBB-SOI)-based MOSFETs can modulate the transistor threshold voltage using the back-gate bias, unlike conventional FinFETs. This unique UTBB-SOI technology attribute has been leveraged to realize compact pseudo-static storage circuits, namely, embedded dynamic random access memory (DRAM) bitcell and a flip-flop operating at 0.2 V and 77 K. This article presents UTBB-SOI device fabrication details and calibrate experimental device characteristics with BSIM compact models. SPICE simulations suggest the feasibility of three-transistor gain-cell embedded DRAM (eDRAM) capable of reliably storing three distinct voltage levels (1.5 bits/cell) and exhibiting retention time of the order of 104 s. Furthermore, a unique pseudo-static flip-flop design is presented, which can lower the clock power by 50%, transistor count by 20%, and static power consumption by 20%.

In this article, we demonstrate an energy efficient convolutional neural network (CNN) engine by performing multiply-and-accumulate (MAC) operations in the time domain. The multi-bit inputs are compactly represented as a single pulse width encoded input. This translates into reduced switching capacitance, compared to baseline digital implementation, and can enable low power neural network computing in an edge device. The time-domain CNN engine employs a novel bi-directional memory delay line (MDL) unit to perform signed accumulation of input and weight products. The proposed MDL design leverages standard digital circuits and does not require any capacitors and complex analog-to-digital converters (ADCs) to realize the convolution operation, thereby enabling easy scaling across the process technology nodes. Four speed-up modes and a configurable MDL length are supported to address throughput versus accuracy trade-off of the time-domain computing approach. Delay calibration units have been accommodated to mitigate the process variation induced delay mismatch among concurrently operating MDL units. The proposed time-domain MDL design implements a LeNet-5 CNN engine in a commercial 40-nm CMOS process achieving an energy efficiency of 12.08 TOPS/W, a throughput of 0.365 GOPS at 537 mV in the 16 speed-up mode. 40-nm CMOS test-chip measurements over 100 MNIST images show 97; classification accuracy. Simulation results over the entire 10 000 MNIST validation dataset images taking into account the circuit non-ideal effects of the MDL-based time-domain approach show a classification accuracy of 98.42;. The test-chip is operational down to the near-threshold voltage (up to 375 mV) while maintaining the classification accuracy over 90; in the 1 $\times $ speed-up mode. Furthermore, two methods of scaling MDLs to multi-bit weights are proposed. Simulation results for 1000-class AlexNet over 50 000 ImageNet validation dataset images show classification accuracy loss within 1; when compared with software implementation. The proposed MDL based time-domain approach performing 1-bit/8-bit weight and 8-bit input MAC operations when compared with the corresponding baseline digital implementations shows 2.09 higher energy efficiency and 2.22 smaller area.