This work shows that a multitier complementary FET (CFET) static random access memory (SRAM) can decouple the area term from PPA-oriented transistor sizing. A topology-aware layout design is used to construct orthogonal and point-symmetric multitier CFET SRAM cells under 1-nm-class design rules, enabling high-density (HD), high-performance (HP), and high-current (HC) sizing at an identical cell boundary. Three-dimensional field-solver extraction identifies a topology-dependent bitline (BL) and wordline (WL) time-constant optimum: the three-tier mapping minimizes the BL time constant while avoiding the superlinear supply-rail resistance penalty observed at four tiers. Back-annotated 128 & times;128 array SPICE simulations show that a three-tier HC 6T SRAM achieves 7.4 & times; read-delay and 2.6 & times; write-delay improvements over the two-tier HD baseline while retaining a 25.0% smaller array-compatible footprint. The same results show that 6T sizing freedom cannot remove the intrinsic read-write stability tradeoff of the shared access path. Extending the layout approach to 8T SRAM adds an independently sized read port, making the read static noise margin (RSNM) equal to the hold static noise margin (HSNM) across the evaluated tier configurations and reducing the read delay by 40%-42% without additional XY-area cost. These results establish multitier CFET SRAM as a layout regime in which area-decoupled transistor sizing becomes a practical circuit-design variable.
Dynamic random access memory (DRAM) scaling toward 4F(2) vertical channel transistors (VCTs) fundamentally reshapes device, array, and circuit-level design tradeoffs. However, the lack of an open-source DRAM device model that is calibrated with recent industry trends prohibits broader innovations in the research community. In this work, we present an "Open DRAM Model" and showcase its application in cross-layer modeling and analysis for 4F(2) VCT, spanning access-device electrostatics, array parasitics, sense margin, disturbance mechanisms, and peripheral integration under a CMOS-bonded-array (CBA) architecture. Based on publicly available disclosures, we construct TCAD-calibrated compact models and array-level frameworks. Our analysis reveals that while 4F(2) VCTs benefit from reduced bitline (BL) capacitance (CBL) and increased initial sense margin, severe BL-to-BL direct coupling emerges as a first-order bottleneck and causes sensing failures. To address this, we evaluate two complementary mitigation strategies: 1) a cell-level partial (half) BL shielding scheme and 2) a circuit-level folded-like twisted BL sense amplifier (BLSA) topology. The proposed half-shield scheme achieves a balanced tradeoff between coupling suppression and CBL inflation, recovering positive sense margin under worst case (6.28 sigma) variability. Furthermore, the folded-like twisted BLSA enables robust sensing even without cell-level shielding, while simultaneously improving sensing latency through effective differential coupling cancellation (nominal random cycle time: baseline D1b 21.5 ns, VCT 12.0 ns). By providing quantitative design guidelines, this work establishes a practical foundation for future 4F(2) VCT DRAM technology pathfinding and system-technology co-optimization.
Processing-in-memory (PIM) by implementing Boolean logic functions in dynamic random access memory (DRAM) has been proposed to alleviate the memory wall problem in data-intensive computing. However, quantitatively evaluating DRAM-based logic operations across different DRAM architectures remains challenging due to the lack of publicly available DRAM cell and peripheral transistor models that accurately capture their behavior. In this work, we present an "Open DRAM Model" that enables comprehensive circuit-level analysis of DRAM operations across multiple architectures, including conventional 6F(2) BCAT, scaled 4F2 VCT, and monolithically stacked 3-D DRAM. The model incorporates both cell characteristics and peripheral sensing circuits, enabling a realistic evaluation of the sense margin and timing behavior. Using this open model framework, we analyze triple-row activation (TRA), a widely studied primitive for implementing majority-based logic in DRAM. Our analysis shows that although TRA inherently reduces the sense margin due to multirow charge sharing, the absence of retention-induced charge loss allows reliable sensing even when tail variations are considered. The results show that TRA remains practically feasible across the evaluated DRAM architectures. We further investigate the practicality of the dual-contact cells (DCCs) scheme for implementing NOT operations. Our analysis reveals that DCC introduces significant layout and routing constraints, making its integration difficult in highly scaled DRAM arrays and vertically stacked 3-D DRAM. To address this limitation, we propose a bitline sense amplifier (BLSA)-level not operation that performs inversion directly within the BLSA, eliminating the need for DCC in the cell array. SPICE simulations across 6F2, 4F2, and 3-D DRAM confirm the correct functionality of the proposed scheme.
Artificial neural networks (ANNs) have enabled major advances in artificial intelligence, yet their growing computational and energy demands challenge conventional von Neumann architectures due to the costly separation of memory and processing. In-memory computing has emerged as a promising solution, particularly through memristive crossbar arrays capable of performing multiply-and-accumulate operations directly within memory. Among nonvolatile memory technologies, magnetic tunnel junctions, the core elements of MRAM, offer high endurance, nonvolatility, and CMOS compatibility, making them attractive candidates for neuromorphic systems. In this work, we report inference results on a 15 x 15 MRAM crossbar, benchmarking experimental measurements against numerical simulations. We further demonstrate hardware-in-the-loop (HIL) training and experimentally validate metaplasticity mechanisms enabling continual learning on simple tasks. These results highlight the potential of MRAM-based in-memory architectures for adaptive, energy-efficient, and scalable artificial intelligence (AI) hardware.
The frequency assignment problem is a nondeterministic polynomial-time hard (NP-hard) optimization problem concerning the assignment of frequency channels to wireless transmitters. Typically, the aim is to minimize interference between transmitters while maintaining a high level of service. In this work, the use of probabilistic d-dimensional bits, or p-dits, for this task is considered. These are stochastic elements that oscillate between discrete states that lie in a multidimensional space. Here, each dimension corresponds to an allowed wireless channel. In addition, a special “0” state exists which corresponds to a disabled and consequently completely noninterfering transmitter. Each transmitter maps to a single p-dit that undergoes repeatable stochastic updates. The p-dit influences the probability distributions of its neighbors, biasing them toward noninterfering states. To provide a realistic and varied dataset, geospatial data for a medium-sized city were used. A simple greedy, Tabu-style, DSatur-style, a traditional p-bit-based probabilistic Ising machine (PIM) solver, and the proposed p-dit-based PIM solver were tasked with finding an assignment, which penalized both deactivated transmitters and interference on two-, three-, and four-wireless-channel problems. Overall, for the same nontrivially short runtime budgets, the p-dit PIM solver found the highest quality solutions of all the approaches explored.
Reservoir computing (RC), a computational paradigm inspired by the recurrent neural networks (RNNs), offers a promising framework for efficient temporal processing with minimal training overhead. Hardware implementation of RC primitive requires devices that exhibit short-term memory, nonlinearity, and energy-efficient state-switching dynamics. While emerging nonvolatile memory (eNVM) technologies have been explored as physical reservoirs, their limited endurance and wafer-scale fabrication challenges hinder widespread application for real-time edge-compatible RC systems. In contrast, 1-transistor-dynamic random access memories (1T-DRAMs) have recently gained significant attention owing to their high scalability, low footprint, and high endurance. In this work, we propose the use of 1T-DRAMs as physical reservoirs for computing and temporal signal processing. We show that the inherent charge storage and its temporal decay in the body of 1T-DRAMs owing to the dynamic recombination efficiently emulates the fading (short-term) memory behavior, making it well-suited for RC. Furthermore, networks of the 1T-DRAM physical reservoirs achieve classification accuracy of 82.46% and 85.02% on reduced MNIST and Weizmann human action dataset, respectively.
Spin-transfer torque magnetic tunnel junction (STT-MTJ) is widely recognized as a promising device for computation-in-memory (CIM) architecture due to its advantages, such as simple nonvolatile structure, CMOS compatibility, and scalability. In spite of the advantages, achieving reliable and efficient sensing of STT-MTJ remains a design challenge. This work presents a comparative evaluation and operational assessment of six contemporary current-mode sense-amplifier (SA) circuits for STT-MTJ, namely the precharge sensing amplifier (PCSA), improved PCSA (IPCSA), separated PCSA (SPCSA), reliability enhanced separated PCSA (RESPCSA), reliability-enhanced differential SA (REDSA), and high reliability SA (HRSA) used in hybrid CMOS-MTJ for CIM architecture. The proposed benchmarking framework analyses critical performance metrics, such as power consumption, sensing margin, read delay, transistor count, and read error probability for all the SA circuits. In addition, assessment of tolerance against process- and device-level variations of these SAs has been conducted with an extensive parametric sweep analysis, considering tunnel magnetoresistance (TMR), oxide thickness variations, and transistor sizing using a 1000-run Monte Carlo (MC) simulation. Based on these insights, our study outlines design tradeoffs and provides recommendations for selecting a suitable SA circuit for hybrid STT-MTJ-based CIM structures.
This work demonstrates a compact probabilistic computing system based on a physics-inspired probabilistic bit (p-bit) architecture with 440 interacting spins configured in a chimera graph and occupying 0.44 mm2 of silicon area. Area efficiency is achieved through a current-mode neuron update circuit and a mixed-signal design approach that integrates pitch-matched standard-cell analog blocks with digital logic and a shared power supply network. Device mismatch and process variations arising from this tightly coupled mixed-signal implementation are addressed using a hardware-aware contrastive divergence training framework. By incorporating nonideal circuit behavior directly into the training loop, the system achieves reliable stochastic dynamics without requiring per-device calibration. Measurement results validate robust probabilistic operation across all spins. The chip is evaluated on probabilistic logic functions, including logic gates and full adders, and on combinatorial optimization problems such as max cut. These results demonstrate that learning-enabled compensation of hardware nonidealities enables scalable probabilistic computing architectures. The proposed system demonstrates effective cross-layer codesign across circuit, architectural, and algorithmic levels, supporting emerging nonvon Neumann computing paradigms.
This work presents a comprehensive benchmarking of ternary content-addressable memory (TCAM) implementations using timing-accurate SPICE simulations, systematically comparing conventional CMOS designs with emerging device technologies, including magnetic tunnel junctions (MTJs), ferroelectric tunnel junctions (FTJs), ferroelectric field-effect transistors (FeFETs), and 2-D reconfigurable field-effect transistors (2D RFETs). Key performance metrics, including search delay, search energy, static power, cell area, sense margin, power-supply sensitivity, and CMOS compatibility, are evaluated alongside technology-specific tradeoffs that govern scalability and robustness. The results identify FeFET-based TCAMs as the most balanced and scalable solution, delivering substantial improvements in energy efficiency, search latency, and cell area relative to CMOS baselines. 2D RFET-based TCAMs exhibit advantages in search energy, static power, and footprint; however, these benefits are offset by excessive search latency and limited CMOS compatibility, primarily stemming from material quality and process integration challenges. MTJ- and FTJ-based resistive TCAMs offer moderate gains in area and delay while maintaining strong CMOS compatibility, but suffer from prohibitively high search energy due to static power dissipation in sense amplifiers (SAs) during search operations. This behavior exposes an inherent tradeoff between energy efficiency and robustness in resistive TCAM architectures.
This article explores the efficacy of a unique defect detection mechanism for the FinFET and FDSOI transistors: magnetomodulation of drain current. Using multiphysics technology CAD (TCAD), we model the impact of static and transient magnetic fields on drain current in the following defect-free and defective devices: 1) FDSOI with interface trap defects and 1) FinFET with gate stack defects. To optimize the magnetic field sensitivity of FDSOI, we evaluate the effects of voltage bias and key device parameters, such as gate oxide thickness, buried oxide thickness, and temperature. We investigate the FDSOI under two different magnetic fields, 2 and 10 T, with the resulting drain current decreasing in the linear region by approximately 1.0% and 19.9%, respectively. Furthermore, aging analysis accounting for bias temperature instability (BTI) at 2 T shows minimal drain current change in a ten-year-aged device—0.05% for NBTI and 0.07% for PBTI. This underscores the limited current magnetomodulation in FDSOI. For the FinFET gate-defect analysis, Ion/Ioff reduces by 0.04% for the same defective device in the presence and absence of a magnetic field. The analysis concludes that the resulting differences in magnetomodulated drain current at 2 T are insufficient to serve as a reliable diagnostic marker for the devices under consideration and the specific bias conditions. Nonetheless, this work introduces and rigorously investigates a novel diagnostic strategy, highlighting possible avenues for further exploration in advanced semiconductor technologies at higher magnetic fields.
Compute-in-memory (CiM) accelerators perform matrix vector multiplications (MVMs) directly inside memory arrays, reducing data movement and improving both energy efficiency and throughput for artificial intelligence (AI) workloads. To reduce the number of conversions, recent designs use multibit compute cells. Nevertheless, practical multibit CiM still faces a tension among accuracy, efficiency, and rewriteability, since multilevel NVM-based designs suffer from nonlinearity and poor rewriteability, while multilevel activation-based DRAM/SRAM macros are limited by mismatch and low accuracy. This work introduces a per-cell DAC-based CiM macro that combines the density of multilevel NVM with fully rewritable DRAM weights to break the tradeoff. Each bit cell embeds a compact 6-bit CTT-based current-mode DAC, calibrated in situ through a write verify write loop, together with a 1T(1C) embedded DRAM. Postlayout simulations of a 576 & times;256 macro in 22-nm FDSOI project 49.9 8 b & sdot; TOPS/W and 8.96 8 b & sdot; TOPS/mm(2), while system-level evaluation on CIFAR-10 and CIFAR-100 with ResNet-50 shows less than 0.2% accuracy loss relative to a digital baseline, without the need for any hardware-aware training.
Artificial intelligence (AI) models are currently driven by a significant upscaling of their complexity, with massive matrix-multiplication workloads representing the major computational bottleneck. In-memory computing (IMC) architectures are proposed to avoid the von Neumann bottleneck. However, both digital/binary-based and analog IMC architectures suffer from various limitations, which significantly degrade the performance and energy efficiency gains. This work proposes OISMA, an energy-efficient IMC architecture that utilizes the computational simplicity of a quasi-stochastic computing (SC) domain (bent-pyramid (BP) system) while keeping the same efficiency, scalability, and productivity of digital memories. OISMA converts normal memory read operations into in situ stochastic multiplication operations with a negligible cost. An accumulation periphery then accumulates the output multiplication bitstreams, achieving the matrix multiplication (MatMul) functionality. A 4-kB 1T1R OISMA array was implemented using a commercial 180-nm technology node and in-house resistive random-access memory (RRAM) technology. At 50 MHz, it achieves 0.789 TOPS/W and 3.98 GOPS/mm2 for energy and area efficiency, respectively, occupying an effective computing area of 0.804241 mm2. Scaling OISMA to 22-nm technology shows a significant improvement of two orders of magnitude in energy efficiency and one order of magnitude in area efficiency, compared to dense MatMul IMC architectures.
Hybrid computation-in-memory (CIM) architecture has emerged as the most promising alternative to overcome the drawbacks of the conventional CMOS-only devices used in the conventional von-Neumann architecture. In the hybrid CIM architecture, a pair of perpendicular magnetic tunnel junctions (pMTJs) is used to store one bit of information. Though there are different methods by which one can store information in the pMTJ pair, the voltage gate spin-orbit torque (VGSOT) is the most prominent due to its advantages over the rest. In this work, a novel write circuit has been proposed that stores information into the pMTJ pair using the VGSOT mechanism. The proposed circuit was implemented and evaluated using the Cadence Virtuoso tool. Comparison of the novel write circuit with the existing one reveals a significant improvement of 77.56% in energy efficiency, 87.01% reduction in delay, 97.09% in energy delay product (EDP), and a 50% decrease in transistor count. Monte Carlo simulations further show that the proposed write circuit achieves lower energy consumption in its worst case than the best-case energy consumption of the existing design, highlighting its robustness and energy efficiency.
The rapid growth of machine learning (ML) workloads, particularly in computer vision applications, has significantly increased computational and energy demands in modern electronic systems, motivating the use of hardware accelerators to offload processing from general-purpose processors. Despite advances in computationally efficient ML models, achieving energy-efficient inference on resource-constrained edge devices remains a significant challenge. The Tsetlin machine (TM) has emerged as an attractive alternative for image classification due to its high throughput and inherently energy-efficient learning paradigm. However, existing TM-based hardware accelerators struggle to balance classification accuracy and energy efficiency, limiting their practical deployment at the edge. This article presents a resource-and energy-efficient convolutional TM (CTM) accelerator with dynamic clause scaling, optimized explicitly for edge field-programmable gate array (FPGA) platforms. The proposed architecture employs LUT-based pipelining and targeted resource-optimization techniques to minimize FPGA resource utilization while maintaining high-energy efficiency and performance. The accelerator is implemented on a Xilinx Zybo-Z20 FPGA and evaluated using the MNIST, Fashion-MNIST (FMNIST), and Kuzushiji-MNIST (KMNIST) datasets, achieving classification accuracies of 97.78%, 85.53%, and 88.54%, respectively, with an energy consumption of up to 0.3 & micro;J per image classification. Compared with state-of-the-art CTM accelerators, the proposed design achieves up to 40 & times; improvements in resource and energy efficiency, demonstrating its suitability for real-time image and pattern classification on edge FPGA-based systems.
In this article, we study the impact of self-heating effects (SHEs) and middle of line (MOL) and back-end of line (BEOL) induced parasitics on multi-tier CFET design, where multiple nanosheet devices are vertically stacked. We analyze and compare the four-tier complementary FET (CFET) design with the conventional two-tier CFET, using TCAD models calibrated to experimental measurements. In addition, TCAD simulations are used to model and analyze SHE-induced heat distribution and temperature profiles and to extract the detailed parasitic RC network from 3-D models of CMOS inverters designed with full MOL and BEOL interconnects. At the device level, the maximum temperature rise (Delta T-MAX) caused by SHE in nFET and pFET devices of the two-tier CFET architecture is 62 and 74 K, respectively. Due to the increased distance from the substrate heat sink, the upper-tier nFET and pFET devices in the four-tier design show higher Delta T-MAX of 83.5 and 98.5 K and more heat trapping in the stacked layers. Furthermore, in the four-tier CFET-based CMOS inverters, the BEOL-induced parasitic RCs are, respectively, 10 and 6.5 times higher in the top-tier than in the two-tier CFET-based inverters. In the bottom tier, the corresponding parasitic RC elements are 6.26 and 2 times higher, respectively, than in the two-tier inverters. Finally, compared to the four-tier design without parasitics, the propagation delay of the top and bottom tier inverters increases by 10% and 8.2%, respectively, due to the interconnect parasitic RCs. For the conventional twotier inverter, the corresponding degradation of delay with parasitic RCs is 37.25%.
The XOR Boolean logic gate is widely used in many applications such as encryption (XOR ciphers), binary addition (half- and full-adders), error detection (parity bits), etc. but is challenging to construct because of its demanding conditional dynamics. It typically requires multiple logic switches or other types of gates, which results in a large gate footprint and low logic density. Here, we present the design of an XOR gate with a single straintronic magnetic tunnel junction which reduces the footprint dramatically. Such a gate is non-volatile and hence suitable for non-von-Neumann architectures, processor-in-memory, etc. The switching time of the gate is 200 ps and the energy dissipation per gate operation is 225 aJ. Cascading of successive stages is accomplished via a CMOS device which plays no role in the gate dynamics but is needed for gain to provide logic level restoration, fan-out and isolation between input and output. This 1 MTJ-1 CMOS design has an energy dissipation that is an order of magnitude smaller than what has been reported for traditional all-transistor XOR designs.
True random number generators (TRNGs) are critical for hardware security, providing unpredictable entropy for cryptographic applications. Spin-transfer torque magnetic tunnel junction (STT-MTJ) devices offer a promising entropy source due to their low-power consumption, nonvolatility, and stochastic switching behavior. This work presents an MTJ-based TRNG that produces three independent bit streams. Two postprocessing architectures are investigated: (a) a three-input majority voter and (b) a two-input two-stage XOR logic. Both schemes are evaluated in terms of entropy enhancement, bias reduction, and hardware efficiency. Simulation results demonstrate that the XOR-based design achieves superior statistical uniformity, while the majority voter provides improved fault tolerance. Both postprocessing approaches, exhibit similar energy consumption approximate to 13.4 pJ/bit while achieving an identical throughput of 25 Mb/s. Randomness quality was validated using the National Institute of Standards and Technology (NIST) SP 800-22 test suite, and comparative analysis highlights the tradeoff between entropy maximization and reliability. The study provides design insights for secure and energy-efficient TRNG implementations in post-CMOS hardware platforms.
Nonvolatile memory devices play a key role in enabling energy-efficient computing. Among them, analog nonvolatile memories such as resistive random access memory (ReRAM) offer high density and low power compared to conventional digital memories. However, their analog nature introduces devicelevel variability that impacts computational accuracy. This work presents the characterization and compact modeling of ReRAM devices fabricated in the SkyWater 130-nm CMOS process. A two-transistor-oneReRAM (2T-1R) structure is used to isolate individual cells and mitigate sneak-path currents. Each cell occupies 4.32 & micro;m(2) , primarily determined by the access transistor sized for microampere-level currents. Statistical measurements are performed across multiple chips to quantify device-to-device variability and conductance distribution. Furthermore, a Verilog-A compact model is developed and calibrated to measured data, capturing nonlinear I-V behavior and variability for accurate circuit-level simulation. The resulting model enables reliable co-design of analog and neuromorphic systems that exploit ReRAM-based computein-memory (CIM) capabilities.
Simulations for the development and optimization of future in-memory computing (IMC) systems often face the problem that the modeling of the large system is desired, but at the same time, the effects at the device level should also be taken into account. Such effects could be due to the material properties and geometries of the nanoscale structures, which are too time-consuming to model in a system-level (SL) simulation. For certain problems and applications, however, it is advantageous or even essential that a high-level model responds to the details of a low-level model. In this article, we present a coupled simulation methodology to overcome this challenge. In a case study, we show the integration of a material-level (ML) memristor simulation, serving as a vector-matrix multiplication (VMM) unit, into an SL simulation. The simulation process between two distributed simulators is controlled by a co-simulation interface (CSI), which we present here. With this co-simulation approach, devices and circuits can be optimized for their application, for example, with regard to energy efficiency. It can also be extended to a multilevel simulation flow.
