The image classification accuracy of a TaOx ReRAM-based neuromorphic computing accelerator is evaluated after intentionally inducing a displacement damage up to a fluence of 10(14) 2.5-MeV Si ions/cm(2) on the analog devices that are used to store weights. Results are consistent with a radiation-induced oxygen vacancy production mechanism. When the device is in the high-resistance state during heavy ion radiation, the device resistance, linearity, and accuracy after training are only affected by high fluence levels. The findings in this paper are in accordance with the results of previous studies on TaOx-based digital resistive random access memory. When the device is in the low-resistance state during irradiation, no resistance change was detected, but devices with a 4-k Omega inline resistor did show a reduction in accuracy after training at 10(14) 2.5-MeV Si ions/cm(2). This indicates that changes in resistance can only be somewhat correlated with changes to devices' analog properties. This paper demonstrates that TaOx devices are radiation tolerant not only for high radiation environment digital memory applications but also when operated in an analog mode suitable for neuromorphic computation and training on new data sets.

In this paper, we test Si vertical-junction disk modulators and waveguide-integrated Ge p-i-n photodiodes (PDs) to see how the key performance metrics are affected by Co-60 gamma radiation (total ionizing dose), a common proxy for simulating a mix of high-energy ion particle flux. It is found that reverse bias dark current increases significantly for both devices after 1-Mrad(Si) exposure. As the bandwidth of the Si disk modulator decreases by 6.5% after 1-Mrad(Si) dose, the bandwidth of the Ge p-i-n PD appears to be unaffected. The increased sensitivity of the Si disk modulator bandwidth to gamma radiation is hypothesized to be caused by a decrease in the carrier concentration of the junction with a resulting increase in the p-n junction RC time constant. The Ge p-i-n PD is relatively insensitive to the surface effects, because the absorption happens away from the SiO2-Ge interface and the gamma radiation has a minimal effect on carrier mobility.

We present heavy ion and proton data on AlGaN high-voltage HEMTs showing single event burnout (SEB), total ionizing dose, and displacement damage responses. These are the first such data for materials of this type. Two different designs of the epitaxial structure were tested for SEB. The default layout design showed burnout voltages that decreased rapidly with increasing LET, falling to about 25% of nominal breakdown voltage for ions with LET of about 34 MeV . cm(2)/mg for both structures. Samples of the device structure with lower AlN content were tested with varying gate-drain spacing and revealed an improved robustness to heavy ions, resulting in burnout voltages that did not decrease up to at least 33.9 MeV . cm(2)/mg. Failure analysis showed that there was consistently a point, location random, where gate and drain had been shorted. Oscilloscope traces of terminal voltages and currents during burnout events lend support to the hypothesis that burnout events begin with a heavy ion strike in the vulnerable region between gate and drain. This subsequently initiates a cascade of events resulting in damage that is largely manifested elsewhere in the device. This hypothesis also suggests a path for greatly improving the susceptibility to SEB as development of this technology goes forward. Testing with 2.5-MeV protons showed only minor changes in device characteristics.

Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.

This conference presents the recipients of the Outstanding Conference Paper Award from the 2015 IEEE Nuclear and Space Radiation Effects Conference.

The recipients of the 2014 NSREC Outstanding Conference Paper Award are Nathaniel A. Dodds, James R. Schwank, Marty R. Shaneyfelt, Paul E. Dodd, Barney L. Doyle, Michael Trinczek, Ewart W. Blackmore, Kenneth P. Rodbell, Michael S. Gordon, Robert A. Reed, Jonathan A. Pellish, Kenneth A. LaBel, Paul W. Marshall, Scot E. Swanson, Gyorgy Vizkelethy, Stuart Van Deusen, Frederick W. Sexton, and M. John Martinez, for their paper entitled Hardness Assurance for Proton Direct Ionization-Induced SEEs Using a High-Energy Proton Beam. For older CMOS technologies, protons could only cause single-event effects (SEEs) through nuclear interactions. Numerous recent studies on 90 nm and newer CMOS technologies have shown that protons can also cause SEEs through direct ionization. Furthermore, this paper develops and demonstrates an accurate and practical method for predicting the error rate caused by proton direct ionization (PDI).

The low-energy proton energy spectra of all shielded space environments have the same shape. This shape is easily reproduced in the laboratory by degrading a high-energy proton beam, producing a high-fidelity test environment. We use this test environment to dramatically simplify rate prediction for proton direct ionization effects, allowing the work to be done at high-energy proton facilities, on encapsulated parts, without knowledge of the IC design, and with little or no computer simulations required. Proton direct ionization (PDI) is predicted to significantly contribute to the total error rate under the conditions investigated. Scaling effects are discussed using data from 65-nm, 45-nm, and 32-nm SOI SRAMs. These data also show that grazing-angle protons will dominate the PDI-induced error rate due to their higher effective LET, so PDI hardness assurance methods must account for angular effects to be conservative. We show that this angular dependence can be exploited to quickly assess whether an IC is susceptible to PDI.

The potential for using the degraded beam of high-energy proton radiation sources for proton hardness assurance testing for ICs that are sensitive to proton direct ionization effects are explored. SRAMs were irradiated using high energy proton radiation sources (~67-70 MeV). The proton energy was degraded using plastic or Al degraders. Peaks in the SEU cross section due to direct ionization were observed. To best observe proton direct ionization effects, one needs to maximize the number of protons in the energy spectrum below the proton energy SEU threshold. SRIM simulations show that there is a tradeoff between increasing the fraction of protons in the energy spectrum with low energies by decreasing the peak energy and the reduction in the total number of protons as protons are stopped in the device as the proton energy is decreased. Two possible methods for increasing the number of low energy protons is to decrease the primary proton energy to reduce the amount of energy straggle and to place the degrader close to the DUT to minimize angular dispersion. These results suggest that high-energy proton radiation sources may be useful for identifying devices sensitive to proton direct ionization.

Single-event upsets are studied in digital logic cells in a radiation-hardened CMOS SOI technology. The sensitivity of SEU to different strike locations and hardening approaches is explored using broadbeam and focused beam experiments. Error distributions in chains of logic flip-flops are studied to determine the impact of various cell designs and hardening techniques on upset uniformity.

Techniques for removing the back substrate of SOI devices are described for both packaged devices and devices at the die level. The use of these techniques for microbeam, heavy-ion, and laser testing are illustrated.

The amounts of charge collection by single-photon absorption (SPA) and by two-photon absorption (TPA) laser testing techniques have been directly compared using specially made SOI diodes. For SPA measurements and some TPA measurements, the back substrates of the diodes were removed by etching with XeF2. With the back substrates removed, the amount of TPA induced charge collection can be correlated to the amount of SPA induced charge collection. There are significant differences, however, in the amount of TPA induced charge collection for diodes with and without substrates. For the SOI diodes of this study, this difference appears to arise from several contributions, including nonlinear-optical losses and distortions that occur as the pulse propagates through the substrate, as well as displacement currents that occur only when the back substrate is present. These results illustrate the complexity of interpreting TPA and SPA single-event upset measurements.

The laser pulse energy thresholds for single-event upset measured by single photon and two photon absorption are measured and compared for Sandia SRAMs and DPSRAMs, and IBM 45-nm SRAMs for devices with and without the back substrate removed. These results are also compared to heavy-ion results taken on the same devices. Sandia SRAM data taken on different test dates resulted in considerably different TPA laser pulse energy thresholds even though the TPA system was calibrated using standard techniques each test date. These differences are believed to be due to changes in laser spot size. This shows that it is imperative to develop a calibration procedure that monitors all relevant laser parameters if TPA is to be used as a routine quantitative tool. Removing the back substrate makes a very large difference in TPA laser pulse energy threshold. This large difference is likely due to either displacement currents generated in the back substrate by TPA and/or nonlinear optical effects which can reduce the laser pulse irradiance in the active region. Nevertheless, the mechanism does not appear to affect the qualitative nature of TPA measurements. Both SPA and TPA laser measurements were used to estimate the heavy-ion threshold LETs of the Sandia DPSRAMs and 45-nm IBM SRAMs. Both SPA and TPA overestimated the heavy-ion threshold LET of the IBM 45-nm SRAMs (likely due to the large laser spot size compared to the size of the SRAM cell), but reasonably estimated the threshold LETs of the Sandia DPSRAMs. For the first time, TPA laser pulse energy (squared) is directly compared to SPA laser pulse energy at threshold. There is reasonable quantitative agreement between the charge required to induce upsets by TPA and SPA with the back substrate removed.

The laser energy thresholds for SEU for SOI 1-Mbit SRAMs built in Sandia's 0.35-μm SOI technology were measured using the two-photon absorption technique. The laser measurements were correlated to heavy-ion threshold LET measurements to determine an empirical relationship between laser energy threshold and heavy-ion threshold LET. This empirical relationship was used to estimate the threshold LETs for other circuits built in Sandia's 0.35-μm SOI technology and SRAMs built in IBM's 45 and 65-nm SOI technologies. For an ASIC built in Sandia's 0.35-μm SOI technology the estimated threshold from laser measurements was close to the measured heavy-ion threshold LET. However, for a dual-port SRAM also built in Sandia's 0.35-μm SOI technology and for 45-nm IBM SOI SRAMs, the threshold LETs estimated from laser measurements did not correlate to the measured heavy-ion threshold LETs. For the IBM SRAMs, the likely cause of the discrepancy between the threshold LETs estimated from laser measurements and the threshold LETs measured by heavy-ion testing is due to the laser pulse simultaneously injecting charge into multiple transistors within a memory cell and/or in adjacent memory cells. This is due to the relatively large size of the laser spot size compared to the size of the SEU sensitive volume of the IBM SOI devices. The hardness assurance implications of these results are discussed.

The effects of moisture on radiation-induced charge buildup in the oxides of a 0.35 μm SOI technology are explored. Data show no observable effects of moisture-related aging on radiation hardness. These results are in contrast to those of previous work performed on bulk MOS technologies fabricated in the 1980s. The cause of these differences do not appear to be due to differences in final chip passivation layers. Instead, other processing variables (including the use of different implant materials and thicker overlayers) may account for these differences. In any case, the SOI technology results indicate that not all advanced technologies exposed to moisture are necessarily susceptible to significant long-term radiation-induced aging effects.

Transistors and ICs built in several different captive and commercial facilities were exposed to moisture, irradiated, and annealed. The moisture exposures were performed using highly accelerated stress test (HAST) at 130degC and 85% relative humidity. Irradiation of n-channel transistors exposed to HAST followed by a long-term anneal resulted in some increase in interface-trap and oxide-trapped charge buildup. However, exposing p-channel transistors to HAST preirradiation resulted in extremely large and unexpected voltage shifts immediately following irradiation. They were observed for devices with either doped oxide or nitride final chip passivation. Because of this, nitride passivation may not be sufficient to prevent H2O from causing enhanced radiation-induced degradation over long time periods in some devices (e.g., commercial devices with nitride final chip passivation packaged in plastic packages). The smaller voltage shifts for the n-channel transistors may be related to the formation of phosphosilicate glass (PSG) overlying the sources and drains of the n-channel transistors impeding the diffusion of moisture to the gate oxides. It is shown that, the large radiation-induced voltage shifts for the p-channel transistors can lead to enhanced IC parametric degradation and functional failure at lower radiation levels. Large increases in radiation-induced field oxide leakage current were also observed for transistors exposed to HAST preirradiation. Transistors were also annealed (prior to irradiation) and irradiated in H2. Approximately the same level of radiation-induced degradation was observed for n- and p-channel transistors suggesting that the diffusion kinetics for H2 diffusion are considerably different than for H2O diffusion. These results raise the concern that exposure of devices to moisture or hydrogen can lead to long-term radiation-induced aging effects.

Abstract We report on recent studies of the effects of 50 keV focused ion beam (FIB) exposure on MOS transistors. We demonstrate that the changes in transistor parameters (such as threshold voltage, Vt) are essentially the same for exposure to a Ga+ ion beam at 30 and 50 keV under the same exposure conditions. We characterize the effects of FIB exposure on test transistors fabricated in both 0.5 μm and 0.225 μm technologies from two different vendors. We report on the effectiveness of overlying metal layers in screening MOS transistors from FIB-induced damage and examine the importance of ion dose rate and the physical dimensions of the exposed area.

We have developed a semi-automated method for determining the series resistance profiles of dot capacitors and for obtaining corrected oxide fields at breakdown. This method is based upon a least-squares-fit of IV data, obtained from a voltage-ramp test, to the Fowler-Nordheim leakage model. The profiles provide insight into the general characteristics of series resistance. Certain features of the profiles can be associated with charge trapping and the onset of oxide breakdown.

We have developed a semi-automated method for determining the series resistance profiles of dot capacitors and for obtaining corrected oxide fields at breakdown. This method is based upon a least-squares-fit of IV data, obtained from a voltage-ramp test, to the Fowler-Nordheim leakage model. The profiles provide insight into the general characteristics of series resistance. Certain features of the profiles can be associated with charge trapping and the onset of oxide breakdown.