Interposer based 2.5D systems have gained popularity to integrate chips and chiplets of advanced logic and stacked memory of high bandwidth memory (HBM) for performance-oriented artificial intelligence (AI) high performance computing (HPC) systems. The size of the interposer is one of the key indices for this technology. At a given transistor density, a larger interposer area means the capacity to carry a higher number of transistors within a package, which directly contribute to the overall performance gain for technology advancement. In this paper, we propose and demonstrate a new CoWoS interposer structure to realize an unprecedented interposer area of $\sim 4000\text{mm}^{2}$ . This is achieved by a multiple layers of supercarrier redistribution layers (SC-RDL) at the backside of LSI (local Si interconnect) interposer of CoWoS-L. The SC-RDL's fan out to an area the same as the organic substrate so that the key technology challenges associated with interposer at this size range are greatly mitigated. These include the difficulty of oS (on substrate) assembly, C4 bump pitch scaling, package reliability margin, and high package coplanarity issues. The structure has been demonstrated on mechanical samples of a 91 mm $\mathrm{x} \ 91$ mm package. Excellent package coplanarity and structure stability as checked by multi-reflow are reported. It also holds the potential to simplify the routing layers in the organic substrate by fanning out the IO's to cover the entire substrate. In addition to achieving the interposer dimension scaling continuously, the SC-RDL based CoWoS-L with the extended area also promises to accommodate more embedded passives and optical engines required in a CPO (co-packaged optics) structure.

Chip-on-wafer-on-substrate (CoWoS®) is an advanced packaging technology to make high performance computing (HPC) and artificial intelligence (AI) components. As a high-end system-in-package (SiP) solution, it enabled multi-chip integration in a side-by-side manner within a compact floor plan than traditional multi-chip module (MCM). Scaling up of the interposer area is one of the key attributes to accommodate more active circuits and transistors into the package to boost the SIP system performance. CoWoS-S based on Si interposer has been developed up to an interposer area of 2500 mm 2 by four-mask stitching. However, the unprecedented interposer area poses major yield and manufacturing challenges. Ways to overcome the Si interposer size limitation becomes highly desirable. In this paper, we introduce CoWoS-L, a new architecture in the CoWoS family, to address the large Si interposer defect-driven yield loss concern. The interposer of CoWoS-L includes multiple local Si interconnect (LSI) chip lets and global redistribution layers (RDL) to form a reconstituted interposer (RI) to replace a monolithic silicon interposer in CoWoS-S. The LSI chiplet inherits all the attractive features of Si interposer by retaining sub-micron Cu interconnects, through silicon vias (TSV), and embedded deep trench capacitor (eDTC) to ensure good system performance, while avoids the issues associated with one large Si interposer, such as yield loss. Furthermore, through insulator via (TIV) is introduced in the RI as vertical interconnect to provide a low insertion loss path than TSV. CoWoS-L with 3x reticle size (~2500 mm2) interposer carried multiple SoC/chiplet dies and 8 HBMs has been successfully demonstrated. The electrical characteristics and component level reliability are reported. The stable reliability results and excellent electrical performance indicate that the CoWoS-L architecture will continue the scaling momentum of CoWoS-S to meet the demand of future 2.5D SiP systems for HPC and AI deep learning.

One of the prominent challenges for widespread adoption of silicon photonics (SiPh) technology is the availability of an integration platform that can simultaneously meet a wide range of power, performance, and cost criteria in different applications. As a result, there is a diversity of SiPh integrated solutions proposed or demonstrated, but none is considered as a common solution. In this paper, we will first survey industry proposed photonic engine structures in monolithic and heterogeneous integration on their strengths and weaknesses. We will then propose a compact and universal PE structure - COUPE (COmpact Universal Photonic Engine) that could consolidate different requirements onto the same integration platform. COUPE has the electrical IC - photonic IC integration with the electrical interface designed to minimize the EIC-PIC coupling loss. Compared with industry proposed PE technology, COUPE can provide low insertion loss for both grating coupler (GC) and edge coupler (EC). For either GC or EC, the COUPE is a solid structure without cavities or mechanically weak parts, thus enabling low insertion loss without contamination or mechanical concerns. COUPE also has the flexibility to be integrated easily with host ASIC to form a co-package structure. The COUPE integration scheme can meet the most demanding system requirements and pave the way for SiPh-based wafer level system integration (WLSI) for high performance computing applications.

Chip-on-Wafer-on-Substrate with Si interposer (CoWoS-S) is a TSV-based multi-chip integration technology that is widely used in high performance computing (HPC) and artificial intelligence (AI) accelerator area due to its flexibility to accommodate multiple chips of SoC, chiplet, and 3D stacks such as high bandwidth memory (HBM). The interposer size increases steadily over the past few years, from one full reticle size (~830 mm 2 ) to two reticle size (~1700 mm 2 ). The growth of interposer size offers more integration power to accommodate more active silicon in a package to satisfy the HPC/AI needs. In this paper, we report the new 5 th generation CoWoS-S (CoWoS-S5) based on a Si interposer as large as three full reticle size (~2500 mm 2 ) by a novel 2-way lithography stitching approach. This will accommodate a multiple of logic chips at a total area of 1200 mm 2 (with chiplets) together with eight HBM stacks. Besides the dimensional increase of the Si interposer, new features are incorporated to further enhance the electrical and thermal performances of CoWoS-S5 compared with the previous CoWoS-S portfolio. These include an integrated deep trench capacitor (iCap) for enhanced power integrity, 5 layers of sub-micron Cu interconnect with reduced sheet resistance to satisfy high speed die to die interconnect, new TSV structure interposer for both return and insertion loss reduction, and a higher thermal conductivity thermal interface material (TIM) to achieve a lower thermal resistance. Component level reliability with excellent electrical and physical results are also discussed.

A logic-HBM2E power delivery system on a chip-on-wafer-on-substrate (CoWoS) platform with a deep trench capacitor (DTC) has been designed and analyzed for high performance computing (HPC) applications. The DTC integrated in the silicon interposer of the CoWoS provides the capacitance density of 300 nF/mm 2 and low leakage current of <1 fA/μm 2 . The impact of the DTC on power integrity of the logic-HBM2E system is investigated. In the logic core area, the system power delivery network (PDN) impedance and the 1 st voltage droop for the CoWoS with the DTC are 93% and 72% lower than those without the DTC. For the HBM2E PHY area, the PDN impedance and simultaneously switching noise (SSN) of VDDQ for the CoWoS with the DTC are 76% and 62% lower than those without the DTC. Moreover, 11.2% and 16.6% unit interval (UI) eye margin are obtained at the data rate of 2.8 and 3.2 Gbps, respectively. These demonstrate the new CoWoS platform with the DTC provides superior power integrity (PI) performance and greatly enhances the system performance for the next generation artificial intelligence (AI) and HPC applications.

To accommodate the exceedingly demanding power integrity (PI) requirements for the advanced artificial intelligence (AI) and high performance computing (HPC) components, high-K (HK) based deep trench capacitors (DTC) have been integrated the first time in the silicon interposer with through silicon via (TSV) and fine-pitch interconnects for chip-on-wafer-on-substrate (CoWoS) integration. A specific capacitance density (C s ) of up to 340 nF/mm 2 is achieved over a large capacitor array, providing a total capacitance (C t ) of up to 68 μF per interposer die. The HK dielectric has intrinsic time-dependent dielectric breakdown (TDDB) lifetime of > 1,000 years at an operation voltage (V cc ) of 1.35V, and a normalized leakage current (I LK ) density < 1 fA/μm 2 under 1.35V at 105° C. No discernable process-induced damage or performance degradation (capacitance, I LK & V bd tailing) were observed. The high capacitance, low leakage, large area and reliability-proven Si-interposer integrated DTC, or iCap, provides superior PI performance and therefore greatly enhances the merit of using CoWoS for the next-generation heterogeneous wafer level system integration (WLSI).

State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200mm 2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accommodate chips of logic and memory and achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approaches such as chip-on-substrate, CoWoS offers more competitive design rule which results in better power consumption, transmission loss, and eye diagram. CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.

High stresses generated from chip-package interactions (CPI), especially when large die is flip mounted on organic substrate using Pb-free C4 bumps, can easily cause low-k delamination. A novel scheme by applying an elastic material can effectively-reduce the transmitted stresses and, thus, resolve the interfacial delamination issue. Along with an optimized chip-package integration solution, a reliable interconnect structure with good electrical performance, has been successfully demonstrated.