10nm M1 local interconnect is using three-color litho-etch-litho-etch-litho-etch (LELELE) integration to enable technology scaling. This paper discusses the challenges to balance the three-color density in critical standard cell scaling, illustrates the limited process margin resulting from iso-dense loading during dry etch CD shrink, and proposes a novel ALD spacer-shrink process which improves iso-dense CD difference by 50%.

As transistor dimension becomes smaller and with the switch to high-k metal gate (HKMG) integration, the need for a sidewall protection layer that is conformal yet meets the low thermal budget requirement becomes critical. In this work, we evaluated PEALD SiN as spacer material in comparison to PECVD SiN, at two different stresses (compressive and tensile) and two different deposition temperatures. Material characterization reveals that PEALD SiN has lower hydrogen impurities, higher density and better resistance against wet chemistry, indicating superior material quality. In addition, film conformality and pattern density characteristics for all PEALD SiN films are significantly improved over PECVD SiN. These improvements in film characteristics help drive improvement in electrical properties for devices with PEALD SiN spacer. (C) 2013 The Electrochemical Society. All rights reserved.

As transistor size continues to shrink, the need for conformal spacer which is insensitive to loading condition arises. Previously we have reported improved device characteristics for transistors with PEALD SiN spacer compared to those with CVD SiN spacer. In this work characteristics of PEALD SiN spacer deposited with liquid or gas precursors is studied. Good device properties are obtained with both precursor types, with slightly better iso-loading characteristics for devices with SiN deposited using liquid precursor.

As we packed more and more transistors into one chip and as the size of transistor continues to shrink, the need for conformal sidewall protection layer becomes critical. In this work improved device properties is demonstrated using PEALD SiN spacer compared to the conventional PECVD SiN spacer.