The state of the art of Technology Computer-Aided Design (TCAD) frameworks for the development of new device structures and their fabrication processes is discussed. A framework must contain support for both integration of existing simulation programs and development of new tools. The complexity and scope of a rigorous TCAD framework requires special effort to create a system which is comprehensible for both users and programmers. The implementation of the task level and user interface of the Viennese Integrated System for Technology CAD Applications (VISTA) is presented, and some important aspects of the integration of independently developed tools are discussed. Particular examples highlight the capabilities of present tools. A 0.25μm fully-planarized CMOS process with shallow trench isolation is studied. The interaction of fairly heterogeneous tools within one common environment becomes thereby transparent. As a second example, the feasibility and the limitations of ultra-low-power CMOS technologies are investigated by simulation. A set of possible ultra-low-power CMOS processes is developed and analyzed for their performance on the gate level. To demonstrate capabilities of new device structures and materials, an analysis of a High Electron Mobility Transistor (HEMT) is presented.

A local maximum in the CGS(VGS) characteristics of an AlGaAs/InGaAs/AlGaAs PHEMT is both calculated by hydrodynamic simulations and extracted from S-parameter measurements. It is found by simulation that the doping on the backside of the channel is the origin of this behavior. VCO measurements demonstrated that this C GS(VGS) characteristic can result in a partially reversed tuning behavior

Combined hydrodynamic/drift-diffusion simulations of GaAs-based pseudomorphic high electron mobility transistors (PHEMTs) are presented. They do not only take into account the structure of the intrinsic transistor but also model the complex geometries of contacts and dielectric passivation in a realistic manner. Special care was taken to implement a general scheme for the T-gate cross section that allows to model gate profiles realized with electron beam lithography as well as with spacer processes based on optical lithography. Measured dc and RF data of two different PHEMTs (gate lengths 220 and 500 mm, respectively) manufactured on the same wafer with spacer technology are calculated very exactly. The simulator is then used to predict the effects of gate length reduction, modification of the T-gate profile and thinning of the passivation on device RF performance quantitatively. The specific problems of gate spacer processes applied to high frequency devices are identified, and the most effective process improvements are indicated.

A method is presented which allows for a unified treatment of interface conditions covering also both extreme cases, Dirichlet and Neumann boundary conditions. This unified treatment is especially useful if the type of the interface condition depends on the internal state of the device. The method is applied to a heterojunction interface where thermionic field emission and tunneling is assumed.

This paper presents new features implemented in the simulation environment VISTA which has been developed in our institute. The basic functionality dealing with the simulation of the manufacturing process and electrical characterization of semiconductor devices was extended by automatic experiment generation, parameter fit and optimization features. An example demonstrates the optimization of the electrical characteristics of vertical double-diffused metal-oxide-semiconductor field-effect transistors using these framework capabilities.

Technology CAD has already proven to be an attractive supplement to standard process development methodologies for VLSI technology. The Vienna Integrated System for TCAD Applications is such a simulation environment which offers great flexibility and a large number of tools for process development. On the other hand smart power devices gain increasingly interest for applications which need to combine low voltage logic and power output devices as, e.g. for automotive electronics. The flexibility of TCAD makes it also applicable for smart power technology to cut down development costs and cycle times

Measurements and simulations of three different pseudomorphic high electron mobility transistors (PHEMT's) are presented. The PHEMT's possess the same epitaxial structure but different geometrical properties. For the simulations, the generic device simulator MINIMOS-NT is employed. This simulator is not restricted to planar device surfaces but is able to model complex surface topologies including the effect of passivating dielectric layers. Mixed hydrodynamic and drift-diffusion simulations are demonstrated. They include the DC characteristics as well as the bias-dependent gate capacitances. Thus, bias-dependent current-gain cutoff frequencies f(T) can be calculated. The results compare very well with the values obtained by small-signal parameter extractions from S-parameter measurements, Although a single consistent set of parameters is used for the simulations of all three devices, their characteristics are reproduced with an accuracy to our knowledge not reported before. Therefore, the DC and RF properties of PHEMT's with geometries significantly different from the measured devices can be reliably predicted.

Simulations and measurements of submicron pseudomorphic high electron mobility transistors (HEMTs) are presented. For the simulations the generic device simulator MINIMOS-NT is used which is capable of dealing with complex device geometries as well as with several physical models represented by certain sets of partial differential equations. A description of the structure of the simulator is given, which shows the basic idea of splitting the device geometry into distinct regions. Within these "segments", arbitrary material properties and physical models, i.e., partial differential equations, can be defined independently. The segments are linked together by interface models which account for the interface conditions. The simulated characteristics of a HEMT with a gate length of 240 nm are compared with the measured data. Essential physical effects which determine the behavior of the device can be identified in the output and transfer characteristics.

Simulations and measurements of a submicron pseudomorphic high electron mobility transistor (HEMT) are presented. For the simulations the generic device simulator MINIMOS-NT [1] is used which is capable of dealing with complex device geometries as well as with several physical models. The simulator allows a simulation of the extrinsic behavior of a HEMT Two different methods of contacting the channel in the simulation are compared, source and drain metal directly contacting the channel versus contact metal only on top of the cap layer. It is shown that one has to include all heterojunctions in the current path to obtain a proper simulation of the transconductance of a HEMT. Moreover, it is shown that hydrodynamic simulation in the channel is also necessary.

The Smart Power Device under consideration is a buried layer device which is widely used in industry. An n-doped epitaxy layer is grown on a highly n-doped buried layer. This layer is placed on the p-substrate. The epitaxy-and buried layers are surrounded by a double diffused p-isolation. The leakage currents between the epitaxy layer and the isolation are simulated and measured in a temperature range from 300 K to 500 K.

The lower bounds of the supply voltage VDD of ultra-low-power CMOS technologies are investigated under the constraints of standard digital circuit design. After discussing the peculiarities of ultra-low-power CMOS processes, low-voltage device operation, and scaling benefits, the lower limits for VDD are narrowed down from two sides. First, a simple inverter based on idealised transistors is investigated analytically to determine a set of absolute lower bounds of VDD for a set of given design constraints, i.e. minimum gain and noise margins. Next, the feasibility and performance of ultra-low-power CMOS technologies are investigated using process and device simulation, followed by post-processing of the simulated I-V and capacitance data, to determine a set of achievable lower bounds of VDD. On the basis of state-of-the-art processes and special scaling, a set of possible ultra-low-power CMOS processes was developed and numerically analysed on the gate level. These numerical data are then related to the analytical results.

Succeeding an earlier paper on the data level, the Viennese Integrated System for Technology CAD Applications (VISTA), an integration and development system for Technology CAD, is presented. Starting with a short overview of TCAD methodology and existing integrated systems, portability and comprehensibility are postulated as key considerations and an application-framework architecture is proposed. The design of VISTA's user interface and task level, presented next, adheres strictly to these guidelines. To enable the cooperation of independent simulation tools, an automatic triangulation-based service is provided by VISTA to resolve inconsistencies in wafer representations. A final example shows how three different simulators, integrated by the framework are used to simulate a planarized, trench-isolated 0.25 /spl mu/m CMOS process.< >

As semiconductor technology continues to evolve, numerical modeling of the electrical device behavior is becoming increasingly important. In this contribution, results of a two-dimensional transient simulation of a charge-coupled device are presented. A hydrodynamic model suitable to describe the high electron mobility transistor is presented as well as simulation results. The concepts underlying the simulation of these rather complex devices are briefly discussed. Models for mobility and heat flux are critically reviewed

This paper will provide information on the features of the new device simulator MINIMOS NT and demonstrate its efficiency in transient simulation of complex device structures. An example will indicate the feasibility of such simulations even on a workstation.

MINIMOS-NT, a generic device simulator is presented. This simulator is capable of dealing with complex device geometries as well as with several physical models represented by certain sets of partial differential equations. A description of the structure of the simulator is given, which shows the basic idea of splitting the device geometry in distinct regions. Within these ``segments'', arbitrary material properties and physical models, i.e. partial differential equations, can be defined independently. The segments are linked together by interface models which account for the interface conditions. The emerging linear system can be solved by a Gauß-solver or by a state-of-the-art BiCGStab algorithm. Two examples, an n-channel CCD and a quarter micron low-noise HEMT, conclude the explanations.

In order to meet the requirements of advanced process and device design, a new generation of TCAD frameworks is emerging These are based on a data level providing a common data interchange format. Such a format must be suitable for building simulation databases, and needs to be accompanied by supporting tools and by a procedural interface with multi-language bindings for data storage and retrieval by application programs. The complexity and scope of a rigorous TCAD framework requires special efforts to create a system which is both transparent to the user and comprehensible to the programmer. A consistent architecture and strict adherence to general software engineering guidelines can contribute significantly to the solution of this problem. We discuss general requirements and architectural issues of the data level, the user interface and the task level environment, and present their implementation in VISTA, the Viennese Integrated System for Technology CAD Applications.

Pseudomorphic submicron High Electron Mobility Transistors (HEMT) have conquered a broad field of application because of their high-frequency performance. The DC characteristics of a 0.23 μm gate length transistor have been calculated by our recently developed device simulator using a hydrodynamic model (HD) which accounts for carrier heating effects in the short channel region. A block iterative scheme combined with a full Newton method is applied to improve the convergence performance, robustness and stability of the HD model. Furthermore, an extended Scharfetter-Gummel scheme was used to account for the spatial variation of material properties such as band edge energy and effective density of states