As design rule (DR) scaling continues to push lithographic imaging to higher numerical aperture (NA) and smaller k1 factor, extensive use of resolution enhancement techniques becomes a general practice. Use of these techniques not only adds considerable complexity to the design rules themselves, but also can lead to undesired and/or unanticipated problematic imaging effects known as "hotspots." This is particularly common for metal layers in interconnect patterning due to the many complex random and bidirectional (2D) patterns present in typical layout. In such situations, the validation of DR becomes challenging, and the ability to analyze large numbers of 2D layouts is paramount in generating a DR set that encodes all lithographic constraints to avoid hotspot formation. Process window (PW) and mask error enhancement factor (MEEF) are the two most important lithographic constraints in defining design rules. Traditionally, characterization of PW and MEEF by simulation has been carried out using discrete cut planes. For a complex 2D pattern or a large 2D layout, this approach is intractable, as the most likely location of the PW or MEEF hotspots often cannot be predicted empirically, and the use of large numbers of cut planes to ensure all hotspots are detected leads to excessive simulation time. In this paper, we present a novel approach to analyzing fullfield PW and MEEF using the inverse lithography technology (ILT) technique, [1] in the context of restrictive design rule development for the 32nm node. Using this technique, PW and MEEF are evaluated on every pixel within a design, thereby addressing the limitations of cut-plane approach while providing a complete view of lithographic performance. In addition, we have developed an analysis technique using color bitmaps that greatly facilitates visualization of PW and MEEF hotspots anywhere in the design and at an arbitrary level of resolution. We have employed the ILT technique to explore metal patterning options and their impact on 2D design rules. We show the utility of this technique to quickly screen specific rule and process choices-including illumination condition and process bias-using large numbers of parameterized structures. We further demonstrate how this technique can be used to ascertain the full 2D impact of these choices using carefully constructed regression suites based on standard random logic cells. The results of this study demonstrate how this simulation approach can greatly improve the accuracy and quality of 2D rules, while simultaneously accelerating learning cycles in the design phase.

As design rules and corresponding logic standard cell layouts continue to shrink node-on-node in accordance with Moore's law, complex 2D interactions, both intra-cell and between cells, become much more prominent. For example, in lithography, lack of scaling of lambda/NA implies aggressive use of resolution enhancement techniques to meet logic scaling requirements-resulting in adverse effects such as 'forbidden pitches'-and also implies an increasing range of optical influence relative to cell size. These adverse effects are therefore expected to extend well beyond the cell boundary, leading to lithographic marginalities that occur only when a given cell is placed "in context" with other neighboring cells in a variable design environment [1]. This context dependence is greatly exacerbated by increased use of strain engineering techniques such as SiGe and dual-stress liners (DSL) to enhance transistor performance, both of which also have interaction lengths on the order of microns. The use of these techniques also breaks the formerly straightforward connection between lithographic 'shapes' and end-of-line electrical performance, thus making the formulation of design rules that are robust to process variations and complex 2D interactions more difficult.To address these issues, we have developed a first-principles-based simulation flow to study context-dependent electrical effects in layout, arising not only from lithography, but also from stress and interconnect parasitic effects. This flow is novel in that it can be applied to relatively large layout clips-required for context-dependent analysis-without relying on semi-empirical or 'black-box' models for the fundamental electrical effects. The first-principles-based approach is ideal for understanding context-dependent effects early in the design phase, so that they can be mitigated through restrictive design rules. The lithographic simulations have been discussed elsewhere [1] and will not be presented in detail. The stress calculations are based on a finite-element method, extrapolated to mobility using internal algorithms. While these types of calculations are common in '1D' TCAD space, we have modified them to handle similar to 10 mu m X 10 mu m clips in reasonable runtime based on advances in software and optimization of computing resources, structural representations and simulation grids.In this paper, we discuss development and validation of the simulation flow, and show representative results of applying this flow to analyze context-dependent problems in a 32-nm low-power CMOS process. Validation of the flow was accomplished using a well-characterized 40/45-nm CMOS process incorporating both DSL and SiGe. We demonstrate the utility of this approach not only to establishing restrictive design rules for avoiding catastrophic context-dependent effects, but also to flag individual cells and identify cell design practices that exhibit unacceptable levels of context-dependent variability. We further show how understanding the sources of stress variation is vital to appropriately anchoring SPICE models to capture the impact of context-dependent electrical effects. We corroborate these simulations with data from electrical test structures specifically targeted to elucidate these effects.

Design rule (DR) development strategies were fairly straightforward at earlier technology nodes when node-on-node scaling could be accommodated easily by reduction of λ/NA. For more advanced nodes, resolution enhancement technologies such as off-axis illumination and sub-resolution assist features have become essential for achieving full shrink entitlement, and DR restrictions must be implemented to comprehend the inherent limitations of these techniques (e.g., forbidden pitches) and the complex and unanticipated 2D interactions that arise from having a large number of random geometric patterns within the optical ambit. To date, several factors have limited the extent to which 2D simulations could be used in the DR development cycle, including exceedingly poor cycle time for optimizing OPC and SRAF placement recipes per illumination condition, prohibitively long simulation time for characterizing the lithographic process window on large 2D layouts, and difficulty in detecting marginal lithographic sites using simulations based on discrete cut planes. We demonstrate the utility of the inverse lithography technology technique [1] to address these limitations in the novel context of restrictive DR development and design for manufacturability for the 32nm node. Using this technique, the theoretically optimum OPC and SRAF treatment for each layout are quickly and automatically generated for each candidate illumination condition, thereby eliminating the need for complex correction and placement recipes. "Ideal" masks are generated to explore physical limits and subsequently "Manhattanized" in accordance with mask rules to explore realistic process limits. Lithography process window calculations are distributed across multiple compute cores, enabling rapid full-chip-level simulation. Finally, pixel-based image evaluation enables hot-spot detection at arbitrary levels of resolution, unlike the 'cut line' approach. We have employed the ILT technique to explore forbidden-pitch contact hole printing in random logic. Simulations from cells placed in random context are used to evaluate the effectiveness of restricting pitches in contact hole design rules. We demonstrate how this simulation approach may not only accelerate the design rule development cycle, but also may enable more flexibility in design by revealing overly restrictive rules, or reduce the amount of hot-spot fixing required later in the design phase by revealing where restrictions are needed.

Lithography simulation has proven to be a technical enabler to shorten development cycle time and provide direction before next-generation exposure tools and processes are available. At the early stages of design rule definition for a new technology node, small critical areas of layout are of concern, and optical proximity correction (OPC) is required to allow full exploration of the 2D rule space. In this paper, we demonstrate the utility of fast, resist-model-based, OPC correction to explore process options and optimize 2D layout rules for advanced technologies. Unlike conventional OPC models that rely on extensive empirical CD-SEM measurements of real wafers, the resist-based OPC model for the correction is generated using measured bulk parameters of the photoresist such as dissolution rate. The model therefore provides extremely accurate analysis capability well in advance of access to advanced exposure tools. We apply this 'virtual patterning' approach to refine lithography tool settings and OPC strategies for a collection of 32-nm-node layout clips. Different OPC decorations including line biasing, serifs, and assist features, are investigated as a function of NA and illumination conditions using script-based optimization sequences. Best process conditions are identified based on optimal process window for a given set of random layouts. Simulation results, including resist profile and CD process window, are validated by comparison to wafer images generated on an older-generation exposure tool. The ability to quickly optimize OPC as a function of illumination setting in a single simulation package allows determination of optimum illumination source for random layouts faster and more accurately than what has been achievable in the past. This approach greatly accelerates design rule determination.

Pushing optical microlithography towards the 32nm node requires hyper-NA immersion optics in combination with advanced illumination, polarization, and mask technologies. Novel approaches in model-based optical proximity correction (OPC) and sub-resolution assist feature (SRAF) optimization are required to not only produce correct feature shapes at the nominal process condition but also to maintain edge placement tolerances within spec limits under process variations in order to ensure a finite process window. In addition, it is becoming increasingly important to consider interactions between multiple layers when performing correction in order to ensure electrical viability. In this paper we discuss the application of a model based process-window-aware and interlayer-aware integrated OPC system on 32nm node patterns. Process window awareness will be demonstrated for main feature correction by taking into account image-based modeling at multiple defocus and dose conditions. In addition, interlayer-awareness will be demonstrated by correction that takes into account the effects of active width on gate CD and of contact overlap with metal, gate, and active. The results show an improvement over "non-aware" OPC in gate CD control, in contact overlap, and in overall process margin. In addition, PW aware correction is demonstrated to prevent potential catastrophic failures at extreme PW conditions.

How to effectively control the critical dimension (CD) is always a hot topic in photolithography. In 65nm node using phase shift mask (PSM) techniques, any factors related to CD variations should not be ignored without full investigation due to the ever-decreasing CD budget. In this paper, we focus on the local CD variation (LCDV) at the gate level within an area of 200μm x 200μm printed on a 193nm exposure tool. In contrast with AWLV (across wafer line variation) and ACLV (across chip line variation), the more localized LCDV implies that it is more dependent on the following three major factors: i) local wafer flatness mainly dominated by STI (shallow trench isolation) steps after CMP (chemical mechanical polishing); ii) effectiveness of OPC (optical proximity correction) covering all transistors with different geometrical shapes in circuit layout and iii) line edge roughness (LER) and line width roughness (LWR) related to photo and etch processes. Although OPC errors, LER and LWR are also very important, the current discussion will be limited in characterizing the relationship between LCDV and STI step-height (S-H) due to the length limitation. The STI S-H between the active surface and the trench oxide surface always exists due to the different material selectivity in the CMP process. The major gate CD influences from STI S-H are strongly correlated to the different geometrical shapes of transistors in circuits, such as single/multi-finger, wide/narrow, interior/exterior-flare and etc. According to our experiments and simulations from both alt-PSM (alternating PSM) and att-PSM (attenuating PSM) processes, the following important conclusions can be derived. a) The gate CDs in two PSM processes show different sensitivities to STI S-Hs in different geometrical shapes of transistors in circuit layout. The alt-PSM process is more sensitive than the att-PSM, especially for isolate gates. This is a shortcoming for the alt-PSM process in effectively controlling the LCDV. b) STI S-H usually makes the CD larger in both PSM processes, especially for the isolated gates in the alt-PSM process. From our observations, it is generally true that the narrower the transistor width, the higher the gate CD will be. However, CD variation trends in the att-PSM process are not so explicit as observed with alt-PSM. c) One should be very careful when trying to improve the CD uniformity by reducing STI step-height by using a blanket etch back because OPC errors are tightly combined with STI step-heights. d) Improving the STI S-H uniformity is always welcome because it will improve the AWLV. e) The narrow isolated gate is the best CD feature to monitor the interaction of AWLV with STI S-H uniformity.

Although lithography equipment and alignment capabilities have evolved significantly since the early stepper days of the 1980’s, the techniques for generating overlay mix and match matrices have remained virtually unchanged. The underlying assumption for traditional mix and match matrices is that the lens signature is the dominant influence in total overlay, and that metrology errors need to be averaged out of the raw data. As step and scan systems were introduced in mid 1990s, improved lens quality has reduced the lens signature errors significantly. However, improvements in stepping accuracy and precision did not keep pace with the rapid reduction in lens distortions. As a result, lens distortion signatures, combined with stepping and scanning repeatability issues, render the traditional “lens distortion matrix” methods for generating mix and match matrices invalid. In this paper several metrology sampling layouts were generated, and demonstrated that with appropriate sampling across known degrees of freedom, it is possible to create a mix and match matrix and modeling more appropriate for 65 nm node alignment tolerances. The mix and match approach captures worst case overlay errors in the matching matrix, and also identifies the root causes of the mix and match error sources between scanners.

As the dimensions of devices shrink and the processing of new devices gets more complex, the requirements for overlay are becoming tighter. Many process elements and previously unmodeled components now dominate the total overlay budget; such as reticle error, alignment-mark quality and design, tool control, alignment system setup and alignment sampling layout, etc. Unmodeled errors (RMSE) consume a larger percentage of the total overlay as the tolerances become tighter. The strategy pursued was to reduce the contribution of each of these elements to as small as possible.In this paper, an improved sampling method is introduced to optimize the sampling layouts in order to minimize RMSE in alignment modeling solutions. The applications of these optimized sampling layouts in both production and system maintenance are also introduced.

A quick, accurate, automatic and robust method to evaluate the best focus and lens quality of the advanced lithography tools is highly demanded when the optical lithography is pushed into 130 nm regimes and beyond. This paper presents how this tedious lithographer's daily job has been performed in Texas Instrument in a more pleasant way thanks to scatterometery. The widely used critical dimension (CID) SEM measurement and +/-10% golden rule have been experiencing in great difficulties to define the optimal process conditions. CID only is not capable to fully describe the resist profile. Lithographers must consider all resist profile parameters such as sidewall angle, resist height and linewidth of resist profile which can be quickly measured by scatterometer. Across exposure field variation, another key process sensitive parameter, has to be integrated into the decision-making loop of process optimization. A new parameter (DCAT ratio) has been introduced and defined as a function of those process sensitive parameters. It has a clear maximum and zero first derivative point (that is, a preferred parabolic bell shape) at the best process condition. The DCAT ratio has been used to find the true best focus offset for multiple scanners to guide tool-to-tool focus matching. It has been used to qualify scanners, optimize lithography process and determine the exposure latitude.

Gate critical dimension (CD) uniformity across field is a key parameter in total gate CD control; it is especially important for highly integrated microprocessor chip with large die size and high speed. Intensive study has been conducted to reveal the impact of scanner leveling tilt, defocus and illumination distribution on CD uniformity across field. Correspondingly CD in die range, vertical-horizontal CD bias, resist side wall angle and profile have all been characterized and monitored for each individual scanner. The monitoring methodology we have established enables us to maintain these CD parameters within fairly tight control range, and also provided efficient and accurate data on tool capability and marginality for running production.

As photolithography processes continue to increase in complexity, in order to maintain anticipated productivity it has become more challenging to increase the throughput, lower the rework rate and improve tool utilization. Manufacturing automation system deployed in a production site provides a source to monitor the photolithography process, the operation efficiency and the health of equipment. However, it is found to be a time-consuming and difficult process to analyze the large amount of data and determine the exact source of productivity hitter. Based on these needs, a new methodology is proposed in this paper to quantify the productivity hitter versus process, operation, and equipment. A tool is developed from this methodology to track through every tool operation time and operation steps based on information of tool event logs (event-based) via network. By applying the tool, an easy to view information can be quickly derived from the event log data, for rapid decision making such as lot disposition, recipe optimization, and equipment function check.The event-based methodology is introduced in this paper. In addition, several examples are studied by using this tool in ASIC type production environment. The effects of track delay, hidden overhead time, poor lot queuing and excessive error-assist time, etc. are studied and quantified. By applying the tool, the time taken to accurately locate the root cause of productivity hitter is significantly reduced. Based on the analysis, the guidelines are given to optimize the tool utilization and raw throughput, and the productivity is improved accordingly. Future works including fully integrated into in-house manufacturing automation are discussed.