This study presents a comprehensive investigation of the impact of the deposition temperature on the HfxZr1−xO2 (HZO) ferroelectric layer of ferroelectric random access memory with TaN electrodes. This investigation mainly focuses on its electrical characteristics and compares the differences. It is revealed that the deposition temperature plays a crucial role in determining the crystal structure of HZO, which can exhibit a combination of tetragonal and orthorhombic phases or exist solely in one of the two phases. Furthermore, the grain size of HZO varies with the deposition temperature. These findings correspond well to the electrical measurement results, including leakage current, polarization, capacitance, and reliability tests. The study tracks the phase transition process during the operation of switching cycles when the phase transition process can be monitored as well. To better understand the observed differences, physical models that shed light on the underlying mechanisms affected by deposition temperature are proposed at the end of the article.

In recent years, GaN HEMT has become one of the most ideal devices for its low ON-state resistance and high breakdown voltage. Compared with other HEMT structures, GaN MIS HEMT is recognized as one of the most attractive candidates to replace silicon-based high-power devices in the aerospace industry because of their excellent temperature tolerance. Therefore, this study investigates how a wide temperature range of 77-393 K influences the degradation mechanism of negative gate bias stress (NGBS) in GaN MIS-HEMTs. The threshold voltage shift for GaN MIS-HEMTs' NGBS is very distinctive both under cryogenic temperature and high temperature. Typically, as the temperature rises from 77 to 303 K, the positive shift of threshold voltage also increases due to electron trapping in the Si3N4 bulk layer and at the Si3N4 /AlGaN interface. However, from 303 to 393 K, the opposite behavior of the threshold voltage shift is observed due to additional hole trapping in Si3N4 from ionization impact, which can be verified from its stress data in Silvaco TCAD simulation and its recovery duration as well. In addition, a thicker Si3N4 layer device is produced to clarify the NGBS model. Thus, this study proposes an extensive NGBS model from 77 to 393 K to verify the abnormal degradation phenomenon in GaN MIS-HEMTs.

In this study, electrical measurements on ferroelectric random-access memory by prior x-ray irradiation are conducted. Compared with an unirradiated device, parameters such as current leakage and remnant polarization of the irradiated device were unexpectedly improved. Besides, better reliabilities including the number of endurance times and retention time have also been demonstrated. To clarify the underlying physical mechanism, the electrical properties are analyzed. The current-voltage curve (I-V) implies a change in the grain size in the ferroelectric layer (FL), and the capacitance-voltage curve (C-V) profile indicates that the FL undergoes a phase change during irradiation. Finally, according to the electrical results, a physical model is proposed as an explanation.

In this study, the reliability issues are discussed under dc and ac negative gate bias stress (ac-NGBS) in Al2O3 /SiN4 metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). Converse degradation between these two stress conditions is discovered. The holes generated by trap-assisted thermionic field emission (TA-TFE) are trapped into the Al2O3 layer, so that the threshold voltage ( V-th ) decreases under dc negative gate bias stress (dc-NGBS). V-th increases because of the hot electrons injected into the GaN layer, while the device is turned on quickly under ac-NGBS. In addition, the degradation mechanisms under dc-NGBS and ac-NGBS are confirmed by the OFF-state gate and drain leakages, respectively. Silvaco TCAD is used to validate the degradation mechanism under ac-NGBS. Finally, the characteristics of the V-th shift transition from dc to ac NGBS are discussed.

Previous studies have reported the formation of n+ regions in amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) upon doping hydrogen (H) to the AOS channel layer from the deposition atmosphere of overlayer passivation / interlayer dielectrics (ILD) e.g. by hydrogenated plasma-enhanced chemical vapor deposition. Thus, self-aligned coplanar TFT structures can be easily formed. However, H-doping causes indiffusion into the channel, thus shortening the actual channel length from the designed size, resulting in a type of “short-channel effect.” In this work, we applied bottom-gate oxide engineering wherein N 2 O plasma treatment on a bottom-gate oxide suppresses the hydrogen diffusion to the amorphous IGZO (a-IGZO), thus minimizing the short-channel effect. The lateral hydrogen diffusion length can be remarkably reduced from 1.44 to 0.26 μm. Additionally, a current stress stability test was conducted. The current–voltage and capacitance–voltage results show that the use of bottom-gate oxide engineering improved the reliability of the IGZO TFTs.

We examined the effect of backside insulation on the dynamic on-resistance of lateral p-GaN HEMTs. To gain a comprehensive understanding of the dynamic onresistance difference between substrate grounded and substrate floating p-GaN HEMTs, we conducted in-circuit double pulse testing and long-term direct current (DC) bias stress. We have realized that while backside insulation can enhance the breakdown voltage of lateral p-GaN HEMTs, it also comes with a tradeoff in device reliability. Results through Sentaurus TCAD simulation suggest that the use of backside insulation in devices gradually disperses potential to the buffer barrier. As a result, the potential barrier at the buffer edge of the 2DEG channel decreases significantly, leading to considerable electron trappings at buffer traps. This breakdown voltage and reliability tradeoff also applies to HEMT technologies using insulating substrates.

In this study, the reliability issues are discussed under dc and ac negative gate bias stress (ac-NGBS) in Al $_\text{2}$ O $_\text{3}$ /Si $_\text{3}$ N $_\text{4}$ metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs). Converse degradation between these two stress conditions is discovered. The holes generated by trap-assisted thermionic field emission (TA-TFE) are trapped into the Al $_{\text{2}}$ O $_{\text{3}}$ layer, so that the threshold voltage ( $\textit{V}_{\text{th}}$ ) decreases under dc negative gate bias stress (dc-NGBS). $\textit{V}_{\text{th}}$ increases because of the hot electrons injected into the GaN layer, while the device is turned on quickly under ac-NGBS. In addition, the degradation mechanisms under dc-NGBS and ac-NGBS are confirmed by the OFF-state gate and drain leakages, respectively. Silvaco TCAD is used to validate the degradation mechanism under ac-NGBS. Finally, the characteristics of the $\textit{V}_{\text{th}}$ shift transition from dc to ac NGBS are discussed.

In this study, the reliability issues are discussed under dc and ac negative gate bias stress (ac-NGBS) in Al <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_\text{2}$</tex-math> </inline-formula> O <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_\text{3}$</tex-math> </inline-formula> /Si <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_\text{3}$</tex-math> </inline-formula> N <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_\text{4}$</tex-math> </inline-formula> metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs). Converse degradation between these two stress conditions is discovered. The holes generated by trap-assisted thermionic field emission (TA-TFE) are trapped into the Al <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> O <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{3}}$</tex-math> </inline-formula> layer, so that the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\text{th}}$</tex-math> </inline-formula> ) decreases under dc negative gate bias stress (dc-NGBS). <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\text{th}}$</tex-math> </inline-formula> increases because of the hot electrons injected into the GaN layer, while the device is turned on quickly under ac-NGBS. In addition, the degradation mechanisms under dc-NGBS and ac-NGBS are confirmed by the OFF-state gate and drain leakages, respectively. Silvaco TCAD is used to validate the degradation mechanism under ac-NGBS. Finally, the characteristics of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\text{th}}$</tex-math> </inline-formula> shift transition from dc to ac NGBS are discussed.

In previous research, it has been observed that the threshold voltage (V (TH) ) in IGZO TFTs will shift in the positive direction after the oxygen annealing treatment. However, in this study, IGZO TFTs with an etch stop layer (ESL) structure are annealed with oxygen at 250 degrees C resulting in an abnormal V-TH left-shift in short-channel devices. To better clarify the changes in the device characteristics, the output characteristics before and after annealing are compared. After the oxygen annealing treatment, the current-voltage (I-D-V-D ) output characteristics of the short-channel devices are enhanced, while those of the long-channel devices are degraded significantly, compared to the properties of the pristine devices. These trends in I-D-V-D curves can be further verified through capacitance-voltage (C-V) curves. The rising parasitic capacitance and C-V left shift imply the occurrence of hydrogen diffusion. Precisely speaking, it is the presence of residual hydrogen remaining in the gate insulator (GI) of Si3N4 that causes the changes in the device characteristics after oxygen annealing treatment. Subsequently, the physical models and the energy band diagrams are proposed to elucidate the channel-length-dependent behavior of residual hydrogen diffusion from the gate insulator after the oxygen annealing treatment.

A method of using non-volatile and fast ferroelectric field-effect transistor (FeFET) devices to realize Boolean logic is proposed. First, the internal states are initialized. Then, the gate and body function as input terminals, which are used to write the states of the device, based on the voltage. Finally, the output signals can be easily read through the drain current. Of the 10 Institute of Electrical and Electronics Engineers (IEEE) standard logic gates, eight can be implemented using the proposed operation method alone and by following the definitions listed herein. Thus, to enable FeFET devices to act as functional logic gates, a simple operating method is proposed, providing substantial contributions to the development of computing in memory. The experimental results provide evidence of the efficacy of this method.

This paper investigates the difference in electrical performance and reliability arising from using either titanium nitride (TiN) or tantalum nitride (TaN) as the electrode in ferroelectric random access memories. Because the lattice constant of TaN is better matched to HZO, the TaN-electrode device exhibits better characteristic. However, the leakage of TaN-electrode device increases significantly after wake up. To figure out this phenomenon, current fitting is implemented. According to the fitting results of conduction mechanisms, the existence of oxygen vacancies in the TaN-electrode device provides a reliable explanation to propose models to clarify the degradation mechanisms observed from the TiN- and TaN-electode devices.

In this study, X-ray irradiation of metal–insulator–semiconductor (MIS) AlGaN/GaN high-electron-mobility transistors (HEMTs) is performed. After the X-ray irradiation, the threshold voltage ( ${V}_{\text {th}}{)}$ shift and ON-state current ( ${I}_{\text {on}}{)}$ variation are observed. However, after a recovery period, the degradation trend of ${V}_{\text {th}}$ and that of ${I}_{\text {on}}$ are in opposite directions. Such opposite degradations are demonstrated and explained in this study. As X-rays irradiate the devices, holes, and defects are generated in the GaN layer and Si3N4 layer, respectively. To prove the degradation mechanism induced by X-rays in MIS HEMT, the following characteristics are offered. The drain current ( ${I}_{d}{)}$ and the source current ( ${I}_{s}{)}$ under the X-ray irradiation are introduced to prove the hole generation. The two-step degradation of the gate current ( ${I}_{g}{)}$ after X-ray irradiation provides evidence of the formation of defect states. Moreover, the different degradation behaviors between Schottky-gate HEMT and MIS HEMT are compared and verification of the position of generation of defect states in the Si3N4 layer is given accordingly.

Previous reports on the top-gate IGZO thin-film transistors (TFTs) under negative bias illumination stress (NBIS) show a threshold voltage (VTH) shift to the left. However, in the present study, a right shift in VTHwas observed in the reverse-sweep current-voltage (I-V) curves after applying NBIS to top-gate IGZO TFTs by a UV backlight. The hysteresis window of the forward and reverse sweep I-V curves widened with the increase in the stress time. The abnormal VTHshift and hysteresis-window increment are explained using an energy-band diagram. In addition, an abnormal gm peak appeared in the forward I-V curve after 2000 s of the backlight NBIS, which was verified by testing the devices with different dimensions. Silvaco TCAD simulation results indicated a strong electric field in the sidewall, confirming the generation of sub-channels. The comparison of the Delta VTH after UV backlight NBIS in three different devices suggested that the higher N2O/SiH4 flow rate and lower power deposition can produce a good quality buffer layer. A rapid examination of a buffer layer is possible using the backlight NBIS. In addition, the presence of H2 in the buffer layer was confirmed by the thermal desorption spectroscopy. Finally, the reliability of the devices can be enhanced by improving the modulation of the existing deposition process.

In the past 55 years (1967–2022), the floating-gate memory (FGM) has evolved from a charge-storage concept to become a prime technology driver of the Digital Age. FGM has served as the mainstream nonvolatile memory, enabled the invention or development of all advanced digital systems, and fundamentally changed the world we live in. In this paper, we briefly review the historical development of FGM and project its future trends to the year 2030. As the device dimension is scaled down to the decananometer regime, we expect that many innovations will be made to meet the scaling challenges, and FGM-inspired technology will continue to enrich and improve our lives for decades to come.

Resistance fluctuations are persistent and critical issues in memory device applications. In recent years, several investigations have been conducted to unravel such fluctuations to further improve the retention and endurance of random resistance access memory (RRAM). Elucidating the switching mechanisms and causes of delamination at the insulator/electrode interface during practical bias operations is thus essential for improving RRAM performance. In this work, we first investigated the changes at the Ti/HfO 2 interface in the Ti/HfO 2 /TiN RRAM device for consecutive bias operations. After the negative forming process and the following asymmetric bias operation conditions, the electrical output of the device decreased as a result of abnormal current degradation during iterative set/reset operations, during which the current high-resistance state (HRS) and low-resistance state (LRS) appeared to decrease. Transmission electron microscopy images and energy dispersive spectroscopy point data indicated that titanium oxides are formed at the Ti/HfO 2 interface after asymmetric bias operation compared to the Ti/HfO 2 interface of the pristine device, which provides direct evidence for validating the current degradation. In addition, to verify the influence of the electric fields on the devices during bias operation, we modulated the rising time of the set pulse triangle wavefront to further verify that the formation of TiO x depends on the amplitude of the electric field. Finally, the fitted current results indicate that the conduction mechanism after asymmetric bias operation in HRS and LRS is hopping conduction. Accordingly, a plausible physical model for bias operation in RRAM devices is proposed.

This work proposed extended methods, which can analyze kinds of defects more easily with power spectrum density (PSD) and weighted time lag plot (W-TLP), to decouple single or multi-traps. To get additional high voltage tolerance, it is common to design different kinds of structures dispersing the electric field. In this work, boron and fluorine were doped in the source and drain extension regions to achieve higher voltage operation. However, boron diffusion could worsen the interface quality. Interestingly, after different stress conditions of hot carrier degradation (HCD) and positive bias temperature instability (PBTI), the degradation trends of the two devices show opposite behaviors. It is because the boron can bear the high voltage operation, but also weak the devices’ interface quality. Therefore, to analyze the influence of these defects plays an important role. With Agilent B1530A WGFMU and RTSDataAnalysis software, varied defects response to frequency can be simply detected. It can also use W-TLP to decouple single trap and multi-traps behaviors at the same time.

In GaN-based metal-insulatorsemiconductor high electron mobility transistors (GaNbased MIS HEMTs), Al2O3/Si3N4 bilayer-gate insulator- MIS HEMTs (Al2O3/Si3N4-MIS HEMTs) are considered to have the advantages of low gate leakage and low interface defects. This study will compare Si3N4 gate insulator-MIS HEMTs (Si3N4-MIS HEMTs) to discuss and clarify the abnormal deterioration mechanism of Al2O3/Si3N4-MIS HEMTs under Hot Carrier Effect (HCE). Therefore, in this study, the results of HCE between Si3N4-MIS HEMTs and Al2O3/Si3N4-MIS HEMTs are compared, and the abnormal HCS degradations in Al2O3/Si3N4-MIS HEMTs are discussed and explained in depth. A series of electrical and simulation analysis is conducted in order to verify the degradation mechanism model proposed in this study.

To reduce drain leakage current, carbon doping is introduced in the GaN layer of the p-GaN HEMT device. The focus of this study is on the discussion of the abnormal current behavior that occurs in the saturation region of carbon-doped p-GaN HEMT. This abnormal phenomenon disappears when the device is heated up to 150°C. The abnormal current behavior corresponds to the hot electron stress (HES) result, which indicates that electron trapping causes this abnormal current behavior. An energy band is proposed to describe the lesser trapping effect that occurs in the saturation region.

In this research, the forming-free CBRAM is realized by high pressure hydrogen annealing method (HPHA). With the structure of Cu/HfO2/TiN, the copper will be ionized by the hydrogen ion under the high pressure environment; meanwhile the copper ion will diffuse to the HfO2. Thus, the diffused copper ion can earlier form the precursor seed to generate the filament because of short migration distance. Besides, the characteristic of CBRAM is also improved, which can be explained by the experimental result and the proposed model.

In recent research on memristor of brain-mimicking integrated circuit (IC) architecture, the electrical performance of electrochemical metallization memory can be significantly improved by applying a bilayer switching structure. In this work, a novel amorphous semiconductor InWZnO (IWZO) is used as the main switching layer, and a bilayer structure with HfO2 is fabricated by different deposition technique. By surface and chemical composition analysis, the effect of deposition process and thickness of HfO2 have been fully explored. The bilayer memory inserted with 3 nm HfO2 formed by atomic layer deposition process exhibits excellent electrical properties, such as high endurance cycle (more than 2 x 10(3)), better retention time (up to 2 x 10(4) s, 85 degrees C), relatively uniform resistance state distribution and low compliance current operation. Consequently, the low power electrochemical metallization memory with optimized HfO2 layer has great potential for next generation memory in pixel and three-dimensional brain-mimicking IC technology.