To continue the future of dynamic random-access memory (DRAM) manufacturing with EUV and high NA EUV, alternative techniques for nanofabrication are required to reduce the cost and simplify the processes. In this report, we present the results of the development of a single mask solution with 0.33NA EUV lithography for two important layers, bit-line-periphery (BLP) and storage-node-landing-pad (SNLP), in DRAM manufacturing. The methodology has been established for our examination and assessment of the process window (PW) of the critical dimensions (CD) and the defectivity of the SNLP and BLP layers. Based on this methodology, a pitch 34nm DRAM has been optimized with the spin-on metal oxide resist (MOR) and dark field of a binary mask. We obtained the large overlapping PW of CDs (with a depth of focus of 119nm and an exposure latitude of 25% at a dose-to-size of 89.4mJ cm-2) in the free-defect ranges (20mJ cm-2). We achieved around ~22% dose reduction using the same processes with spin-on MOR applied to the new design of a low-n mask. We observed a pitch of 32nm SNLP and BLP with a single mask layer due to a low-n mask. Additionally, the process window discovery (PWD) methodology for defect inspection in the large area of SNLP and BLP shows good progress which can be applied for optimized conditions. We believe that our results show the resolution limit of 0.33NA lithography for the single mask print SNLP-BLP and 0.55NA EUV is needed for the next generations of DRAM.

Curvilinear design was applied to standard cell layout to improve electrical characteristics and reduce manufacturing costs. Its implementation was intelligently co-optimized with 1-D Manhattan shapes and photolithography process to preserve the standard cell area equivalent to that of 1-D Manhattan-only designs. B-spline curve representation was employed to realize the curvilinear design. Curvilinear pathfinding was carried out through the Voronoi diagram to find the optimum routing path, and the A* routing algorithm to determine the shortest path. In the curvilinear-designed standard cells, the majority of standard cells exhibited reduced total metal length, decreased number of vias, and eliminated the need for an extra metal layer when compared to 1-D Manhattan-only standard cell designs. Manufacturability of curvilinear designs was evaluated, and potential solutions are proposed in the context of design rule, design rules check (DRC) and optical proximity correction (OPC). DRC and OPC were carried out within the currently employed electronic design automation (EDA) tools to verify the curvilinear designs.

High numerical aperture (NA) extreme ultraviolet (EUV) lithography single patterning is evaluated through source mask optimization (SMO). The patterning performance is assessed on random logic metal design with minimum pitches of 24, 22, and 20nm in the horizontal direction to confirm the feasibility of logic metal scaling. We set a 1 square micron as a cell window and choose 200 gauges to include various types of features such as dense, isolated, and tip-to-tip. SMO is performed assuming eight permutations of a) dark-field versus bright-field, b) Ta-based versus low-n attenuated phase-shift masks, and c) with sub-resolution assist feature (SRAF) versus without SRAF. For each design, the process window is estimated.

In this paper we will present initial results for logic and memory features imaged with the TWINSCAN EXE:5000 at the ASML-imec high NA lab after successful etch pattern transfer. For logic applications random logic metal designs (consisting of tight pitches and aggressive tip-to-tips) and corresponding via structures have been characterized for A14 and A10 nodes. As well, bidirectional designs enabled by high NA will be described. For memory applications, results from BLP/SNLP layer for D1d and D0a nodes will be presented.

The integration of curvilinear shapes in semiconductor technology is explored. Curvilinear shapes are classified into forms using Manhattan, rectilinear, and curvilinear representations. The primary objectives of employing curvilinear shapes in Optical Proximity Correction (OPC) and mask technology are identified as error reduction and the effective representation of complex shapes. Leveraging the path optimization characteristic inherent in curvilinear shapes, their utilization was studied for semiconductor layout design. Standard cell design serves as a demonstrative example to highlight these benefits. Using the DTCO Power-Performance-Area-Cost (PPAC) assessment metric, enhancements in both electrical performance and cost efficiency are showcased, compared with designs using Manhattan shapes. We propose a step-by-step adoption strategy of curvilinear design, ranging from restrictive to partial use, and even free-form routing. In addition, we address concerns regarding data volume, outlining how curvilinear representation can effectively mitigate such issues, in OPC, mask technology and layout designs.

We explore high Numerical Aperture (NA) Extreme Ultraviolet (EUV) mask specification for logic metal layer targeting A7 node. A requirement of minimum Critical Dimension (CD) of absorber on mask is investigated by Source Mask Optimization (SMO) and wafer printing simulation for pitch 20nm logic metal pattern in a horizontal direction. The Sub-Resolution Assist Feature (SRAF) horizontal absorber line width needs to be less than 4nm (1X) to avoid being printed on wafer. A minimum absorber line end tip-to-tip is also explored as a key metrics of high NA single patterning limit in Bright-Field (BF) mask with a benefit of low-n attenuated phase-shift mask.

Interfacial Phase Change Memory (iPCM) retrench unnecessary power consumption due to wasted heat generated during phase change by reducing unnecessary entropic loss. In this study, an advanced iPCM (GeTe/Ti-Sb2Te3 Superlattice) is synthesized by doping Ti into Sb2Te3. Structural analysis and density functional theory (DFT) calculations confirm that bonding distortion and structurally well-confined layers contribute to improve phase change properties in iPCM. Ti-Sb2Te3 acts as an effective thermal barrier to localize the generated heat inside active region, which leads to reduction of switching energy. Since Ge-Te bonds adjacent to short and strong Ti-Te bonds are more elongated than the bonds near Sb-Te, it is easier for Ge atoms to break the bond with Te due to strengthened Peierls distortions (Rlong/Rshort) during phase change process. Properties of advanced iPCM (cycling endurance, write speed/energy) exceed previous records. Moreover, well-confined multi-level states are obtained with advanced iPCM, showing potential as a neuromorphic memory. Our work paves the way for designing superlattice based PCM by controlling confinement layers.

The identification of process bottlenecks for emerging nodes is becoming critical in early technology pathfinding. This is chiefly due to the impact of many process parameters on scaling performance. Moreover, quantifying impact of process parameters on scaling performance is of utmost importance since that will determine the ultimate patterning pitches. Edge placement error (EPE) budget is a key limiter for scaling. Previously we introduced a Machine learning based analytics framework to perform impact analysis of various process assumptions on EPE. Here, we extend this framework to forecast key limitations of EUV double patterning for 2025 nodes and beyond. Following the adoption of EUV lithography, the industry is exploring increasing the numerical aperture (NA) to enable high-NA EUV processes. We apply our simulation framework to predict key process sensitivities for controlling EPE for high-NA EUV lithography.

Laser direct-writing enables micro and nanoscale patterning, and is thus widely used for cutting-edge research and industrial applications. Various nanolithography methods, such as near-field, plasmonic, and scanning-probe lithography, are gaining increasing attention because they enable fabrication of high-resolution nanopatterns that are much smaller than the wavelength of light. However, conventional methods are limited by low throughput and scalability, and tend to use electron beams or focused-ion beams to create nanostructures. In this study, we developed a procedure for massively parallel direct writing of nanoapertures using a multi-optical probe system and super-resolution near-fields. A glass micro-Fresnel zone plate array, which is an ultra-precision far-field optical system, was designed and fabricated as the multi-optical probe system. As a chalcogenide phase-change material (PCM), multiple layers of Sb 65 Se 35 were used to generate the super-resolution near-field effect. A nanoaperture was fabricated through direct laser writing on a large-area (200 × 200 mm 2 ) multi-layered PCM. A photoresist nanopattern was fabricated on an 8-inch wafer via near-field nanolithography using the developed nanoaperture and an i-line commercial exposure system. Unlike other methods, this technique allows high-throughput large-area nanolithography and overcomes the gap-control issue between the probe array and the patterning surface.

Rapid changes in the electrical resistance depending on the phases (amorphous and crystal) are one of the most promising bases for universal memory. Phase-change region is spatially inhomogeneous during memory operation in a unit cell because Joule heat for the phase-change is generated at the interface between the metal and compounds. However, delicate optimization of the electrical and thermal properties at the interface is underexplored compared to the bulk. In this study, we modulate the electrical and thermal conductivities by incorporating oxygen in Ag-In-Sb-Te, superior memory compounds where oxygen is chosen for high accessibility and efficiency for the modulation of conductivity. We further analyze the oxidation and crystallization process at the atomic level. Based on the results, we successfully improve the memory performances such as speed, energy, signal ratio, and reliability simultaneously by inserting the oxygenated layer as an interfacial layer. Our study proves that there is considerable room to optimize memory performance at the interface.

Phase-change memory (PCM) is the most promising candidate for next-generation memory devices to replace both dynamic random-access memory and flash memory. Sb2Te3 is a promising phase-change material because of its fast operation speed; however, it has poor thermal stability. The operation mechanism of PCMs is based on the Joule heating process; consequently, sufficient thermal stability is one of the most important factors for scaling PCMs in commercialized devices. Herein, a remarkable increase in the thermal stability of C-incorporated Sb2Te3 is reported. The crystallization and 10-year retention temperatures of C-incorporated Sb2Te3 increased to 66% and 52%, respectively, while a reliable operation speed was maintained as compared to that of Ge2Sb2Te5, an existing commercialized phase-change material for 3D Xpoint memory. Regions with highly incorporated C were observed in the Sb2Te3 crystal grains by transmission electron microscopy. Ellipsometry and X-ray photoelectron spectroscopy revealed increased electron localization caused by interstitial C atoms located between Sb and Te, which effectively hindered grain growth and significantly increased thermal stability. The thermal stability can be further enhanced by adjusting the C content, although some of the device operation characteristics are slightly degraded. This study suggests that Sb2Te3 can be easily and effectively utilized as a suitable material for practical applications involving PCM devices with high thermal stability.

Reversible phase-change is one of the most promising bases to store data for universal electronic memory. Rapid and energy efficient crystallization of Ag-In-Sb-Te, owing to miniscule atomic displacements, has dragged large interest. However, crystallization mechanism at atomic scale and role of element in Ag-In-Sb-Te remain inconclusive. We studied evolution of chemical bonding on crystallization of Ag-In-Sb-Te, i.e., chemical bonding of element In dramatically changes on crystallization from Sb-bonds (In-Sb) to Te-bonds (In-Te). The local environments of In corresponding to In-Sb and In-Te bonds are characterized as InSb-like and AgInTe2-like site, respectively. Further, In largely modulates the degree of atomic ordering and activation energy for crystallization despite of low composition. The overall results suggest that crystallization of Ag-In-Sb-Te is deployed by the transition of local environment of In from InSb-like to AgInTe2-like site. It suggests role of Ag, In, and Te on crystallization, i.e., Ag provides structural flexibility for transition in local environment of In, In disrupts crystallization, and Te assists the other elements to play their respective roles. The present work on the unique crystallization mechanism of Ag-In-Sb-Te successfully accounts for the memory properties depending on composition and can be applied to development of future memory device.

We propose the use of machine learning based analytics to simplify OPC (Optical Proximity Correction) model building process which demands concurrent optimization of more than 70 parameters as nodes shrink. We first built a deep neural network architecture to predict the RMS error, for a given set of model parameters. The neural network was trained on existing OPC model parameters and corresponding output RMS data of simulations to achieve an accurate prediction of output RMS for given set of OPC model parameters. Later. a sensitivity analysis-based methodology for recursive partitioning of OPC modelling parameters was employed to reduce the total search space of OPC model simulations. This resulted in reduction of the number of OPC model iterations performed during model tuning by orders of magnitude.

Phase-change memory utilizing amorphous-to-crystalline phase-change processes for reset-to-set operation as a nonvolatile memory has been recently commercialized as a storage class memory. Unfortunately, designing new phase-change materials (PCMs) with low phase-change energy and sufficient thermal stability is difficult because phase-change energy and thermal stability decrease simultaneously as the amorphous phase destabilizes. This issue arising from the trade-off relationship between stability and energy consumption can be solved by reducing the entropic loss of phase-change energy as apparent in crystalline-to-crystalline phase-change process of a GeTe/Sb 2 Te 3 superlattice structure. A paradigm shift in atomic crystallography has been recently produced using a quasi-crystal, which is a new type of atomic ordering symmetry without any linear translational symmetry. This paper introduces a novel class of PCMs based on a quasicrystalline-to-approximant crystalline phase-change process, whose phase-change energy and thermal stability are simultaneously enhanced compared to those of the GeTe/Sb 2 Te 3 superlattice structure. This report includes a new concept that reduces entropic loss using a quasicrystalline state and takes the first step in the development of new PCMs with significantly low phase-change energy and considerably high thermal stability.

Time-dependent resistance drift in chalcogenide phase change materials is known to cause instabilities in phase-change random access memories (PRAMs). In this study, the resistance drift of the RESET state of GeTe and Ge2Sb2Te5 (GST) nanowires during memory switching was investigated using an optical method to determine the relationship between variation in resistance and time-dependent thermal properties. Changes in morphology and crystal structure were caused by the formation of voids and hillocks in nanowires in the RESET state, which affected the phonon scattering in GeTe and GST nanowires. Consequently, the thermal conduction of the GeTe and GST nanowires in the RESET state was observed to be significantly lower than that in the initial single-crystalline state. Further, it was observed that as the annealing duration of the retention test was increased, the resistance decreased and thermal conduction increased, even though the morphologies of the nanowires were restored to the initial state. These changes were induced by thermally assisted atomic migration, indicating the occurrence of a local structural phase transition in the GeTe and GST nanowires via the formation of voids and hillocks. Our results explain the cause behind the resistance drift observed in GeTe and GST nanowires in the RESET state with bi-polar memory switching characteristics.

Although Sb2Te3, as a candidate material for next-generation memory devices, has attractive properties such as higher operation speed and lower power consumption than Ge2Sb2Te5, its poor stability prevents its application to commercial memory devices. Transition metal dopants provide enhancements in its phase change characteristics, improving both thermal stability and operation energy. However, the enhancement mechanism remains to be sufficiently investigated, and standard properties need to be achieved. Herein, the phase change properties of Sb2Te3 are confirmed to be enhanced by the incorporation of a heavy transition metal element such as Ag. The crystallization temperature increases by nearly 40%, and the operation energy is reduced by approximately 60%. These enhancements are associated with the changes in the local Sb2Te3 structure caused by Ag incorporation. As the incorporated Ag atoms substitute Sb in the Sb-Te octahedron, this turns into a Ag-Te defective tetrahedron with a strong Ag-Te bond that induces distortion in the crystal lattice. The formation of this bond is attributed to the electron configuration of Ag and its fully filled d orbital. Thus, Ag-doped Sb2Te3 is a promising candidate for practical phase change memory devices with high stability and high operation speed.