Ion beam processing applications require adjustments to the process parameters, in order to operate efficiently and with the optimal precision. Global plasma models offer a fast and reliable approach, to characterize and optimize such ion beam sources. In the scope of this work, a self-consistent global plasma model for inductively coupled plasmas (ICPs) using argon as process gas was developed. Targeting surface modification applications in particular, two novel features are implemented and investigated, describing the ion beam extraction process. The plasma boundary above extraction apertures is calculated in an iterative scheme, solving the balance between extracted ions and charge carriers inside the plasma volume self-consistently. Combined with consideration of spatial varying plasma densities, the model is able to predict plasma properties and extracted ion currents for arbitrary ICP systems, extraction geometries and operating conditions. Thereby, multiple ion beam source configurations validate the model, by comparing simulation results with experimentally investigated plasma and ion beam properties, obtained by electrical measurements and Langmuir probe diagnostics in the low pressure environment ( pch=0.06-0.12Pa) of multiple vacuum chambers.

The discovery of two-dimensional materials has revolutionized condensed matter physics, with transition metal dichalcogenides (TMDCs) offering tunable electronic and optical properties. Monolayer tungsten diselenide WSe $_2$ , a direct bandgap semiconductor with strong excitonic effects, is especially promising for optoelectronics. When two WSe $_2$ monolayers are stacked with controlled twisting angles, the resulting twisted bilayer (tB) material forms a moiré superlattice that significantly modifies its electronic structure and optical response through interlayer coupling and band reconstruction. In a systematic study employing photoluminescence (PL) and differential micro-reflectance contrast ( $\mu$ RC) spectroscopy and supported by first-principles calculations, we investigate the optical properties of tB WSe $_2$ for twisting angles $ 0^\circ \lt \theta \lt 60^\circ $ . Excitonic peaks (A, B, C, D) exhibit angle-dependent energy shifts. Notably, A and C excitons show characteristic energy splittings that reflect twisting-angle-modulated interlayer hybridization and spin–orbit coupling effects. The A exciton shows local minima at $0^\circ$ and $60^\circ$ , and a maximum near $30^\circ$ . This pattern reflects variations in interlayer hybridization—stronger coupling at $0^\circ$ and $ 60^\circ$ , weaker at intermediate angles—consistent with moiré-induced modifications. Our work reveals the periodic modulation of exciton energies in WSe $_2$ homo-bilayers across a wide range of twisting angles, directly linking these variations to interlayer coupling strength and spin–orbit splitting. Our findings provide clear experimental–theoretical consistency, identifying the twisting angle as an effective tuning knob for excitonic transitions and interlayer interactions in TMDC bilayers. The work contributes to the understanding of the structure–property relationships in twisted TMDC materials, and the results may lead to new design principles for next-generation, moiré-engineered optoelectronic and quantum devices.

FluidFM deposition, also known as pressure-controlled and force-controlled micropipetting, of nanomaterials suspended in fluidic carrier liquids is known as a capillary-driven, high-precision liquid-in-liquid deposition and manipulation technique in biofluidic environments. In this work, we report on its usage as a liquid-on-solid structuring technique from an aqueous dispersion of colloidal inorganic semiconductor Ag-In-S quantum dots (QDs) stabilized with glutathione ligands on solid substrates. We show the recurrent deposition (3 x 3 matrix) and characterization of three-dimensional liquid-in-air deposits formed by structured sedimentation of the QDs on gold-coated glass substrates upon FluidFM deposition via bottom-up self-assembly. As critical facts for a successful deposition of the QDs turn out: The aqueous nature of the dispersion, the possibility for its careful adjustment regarding density and composition, and an effective surface energy engineering of both the FluidFM cantilever and the gold-coated glass substrates mediated by chemical vapor deposition and physical vapor deposition, respectively. This way, the minimal lateral dimensions of the obtained deposits were (500 +/- 40) mu m, with evaporation-limited contact-line widths of (2.0 +/- 0.5) mu m.

This work presents the development and implementation of a low-temperature atomic layer deposition (ALD) process for metallic cobalt thin films. The works are based on a set of five different Co precursors with alkyne ligands. Computational analysis identified CoCOhept([Co2(CO)6HC≡CC5H11]) as the most promising candidate among a series of potential precursors. Using density functional theory calculations, we examined the surface chemistry of Co2(CO)6HC≡CCH3 during Co ALD. The precursor undergoes dissociative adsorption on Co(001), followed by efficient ligand removal via a hydrogenation reaction with surface H atoms. Simultaneously to the process development with CoCOhept, the chamber geometry has been co-optimized using computational fluid dynamics simulation. By this, the chamber height was identified as a critical factor for a homogenous precursor distribution. We show that a minimum height is mandatory in order to avoid local concentration hot-spots under the gas inlets. The predictions by the model are in good agreement with experiments employing varying chamber geometries. Further experimental tests show the influence of the precursor flow and the plasma pulse duration. We demonstrate the integration of the process in high aspect-ratio silicon structures and on temperature sensitive 3D-photoresist structures.

In this study, the low-temperature bonding of lithium tantalate (LiTaO 3 )-to- silicon (Si) was investigated using plasma activation. In detail the influence of different plasma parameters on the resulting bond was characterized.

In this study, the low-temperature metal bonding of aluminum (AI) was investigated using an in-situ surface passivation. Specifically, the influence of a passivation layer was investigated with regard to sufficient reduction in the aluminium oxide layer. Bonding was performed on both unpatterned and patterned wafers, evaluating interface quality using scanning acoustic microscopy (SAM), scanning electron microscopy (SEM) and shear test.

Energy dissipation through physical downscaling towards more complex types of memory and logic devices, loss of ultrapure water and consumption of large amounts of (toxic) chemicals for wafer cleaning processes, as well as high thermal budget of solid-state synthesis and thin film growth of standard semiconductors including the use of rare earth elements - all this poses great challenges for semiconductor materials science and technology. Therefore, research and development of alternative methods for micro- and nanofabrication and chemical functionalization of a new type of resource- and energy-efficient semiconductors as the core component of every computer chip is crucial. One of the promising opportunities is the transformation of today's complementary metal-oxide-semiconductor (CMOS) electronics into ecofriendly and neuroinspired electronics driven by molecular design and multi-level switching mechanisms at room temperature. The sustainable chemical technology of electron transport and switching materials in semiconductor manufacturing and the development of devices with new unconventional nanophysics, improved performance, and augmented functionalities (beyond-CMOS and More-than-Moore) is becoming increasingly important in the context of a gradual transition to a future-oriented concept of Internet of Everything (IoE). In this article, we focus on the technological significance of semiconductor preparation from single-source (molecular) precursors and the prospect of functionalizing semiconductors using DNA origami nanotechnology and stimuli-responsive metal-oxygen cluster ions such as polyoxometalates (POMs). We also describe the advanced characterization of these qualified molecular systems by soft X-rays. We emphasize the technical relevance of using solution-based methods for the bottom-up preparation of novel and hybrid semiconductors as well as their challenging scalability and the compatibility of methods of molecular technology with lithography-based mass production. Our article aims to contribute to the achievement of the United Nations' Sustainable Development Goal 9 (Industry, Innovation and Infrastructure).

Hybrid bonding is critical for achieving high-quality interconnects necessary for fine-pitch integration, offering superior I/O density, enhanced power efficiency, and improved signal speed compared to other methods. The process involves embedding copper interconnects in dielectric materials, followed by a two-stage chemical mechanical polishing (CMP) to prepare the surface. The final surface must meet stringent criteria, including controlled copper dishing, dielectric erosion, surface roughness, and consistency in via profiles. This study examines the impact of various dielectric materials on the metal CMP process, using atomic force microscopy (AFM) to measure dishing and roll-off as pitch scales from 5 mu m to 1 mu m. The materials analyzed include Silicon Oxynitride (SiON), Silicon Oxide (TEOS), high-density Silicon Nitride, and high-density Silicon Oxide deposited via inductively coupled plasma.

Aluminium to Aluminium (Al-Al) direct bonding is CMOS line compatible and is comparable to gold (Au) and copper (Cu) due to metal cross-contamination in a process line. The Au-Au and Cu-Cu direct bonding are widely used and oxides of these metals are either negligible or can be controlled. Aluminium low temperature direct bonding would enable integrations of various types of sensors onto a CMOS wafer. On the contrary, Al tends to form an oxide layer as soon as it comes in contact to ambient atmosphere, which is difficult to remove and passivate thus requiring higher bonding temperature and bonding forces. In this paper, we would like to present the technology enabler processes that could lead to successful aluminium hybrid bonding: aluminum electro-plating for via filling, aluminum oxide removal and surface passivation and aluminium direct bonding at low temperatures. Lowtemperature bonding is demonstrated using, in-situ surface treatment leading to metallic bonds at a temperature < 300 degrees C in ambient conditions.

This paper focuses on the development of electroplating on 150 mm wafer level for microsystem technology applications from 1-Ethyl-3-methylimidazolium chloride (EMImCl) with Aluminumtrichloride (AlCl3). The deposition was carried out on 150 mm wafers with Au or Al seed layers deposited by physical vapor deposition (PVD). The electrodeposition was carried out using pattern plating. On the Au seed layer, bipolar pulse plating was applied. Compared to the Au seed layer, the electrodeposition on the Al seed layer was favorable, with lower current densities and pulsing frequencies. Utilizing the recurrent galvanic pulses and avoiding ionic liquid convection, inhomogeneities lower than 15% were achieved with a laboratory plating cell. One major aspect of this study was the removal of the native Al oxide prior to deposition. It was investigated on the chip and wafer levels using either current- or potential-controlled removal pulses. This process step was affected by the plasma treatment of the wafer, thus the surface free energy, prior to plating. It turned out that a higher surface free energy hindered proper oxide removal at a potential of 3 V. The theory of oxide breakdown based on electrostriction force via the electrical field was applied to discuss the findings and to derive conclusions for future plating experiments.

Aluminum-to-Aluminum (Al/Al) bonding is critical for wafer-level packaging and heterogeneous integration in modern CMOS compatible semiconductor technologies. Due to electronic devices become smaller and more complex, Al/Al bonding offers a scalable solution with improved thermal management with good electrical performance. Recent advances in low-temperature thermal compression bonding highlight the potential for reliable, high-throughput integration, establish Al/Al bonding a key enabler of semiconductor technology. Due to the property of forming a strong oxide, high temperatures and pressures are typically required to create successful Al-Al bonding at wafer level. In this study, a low-temperature thermocompression bonding process for aluminum limited to a maximum temperature of 350 degrees C is investigated. In contrast to conventional processes, no wet chemical treatment is used to remove surface oxides on the aluminum. Instead, an in-situ PVD deposition technique is used in which an ultra-thin layer of precious metal is applied to prevent oxidation of the aluminum. Titanium is chosen next to palladium specifically for its role in passivating the aluminum surface to ensure improved stability and prevent unwanted oxidation effects during the bonding process. In this study, an additional layer under the aluminum is also being investigated to reduce the surface roughness of the aluminum. This layer is strategically introduced to improve the overall roughness and quality of the aluminum surface to address important aspects of the bonding process. Thermocompression bonding was performed on both unpatterned and patterned wafers, with the patterned wafers using 60 mu m and 80 mu m wide frames for bonding. The subsequent investigations included the evaluation of the interface quality by atomic force microscopy (AFM), scanning electron microscopy (SEM) and the evaluation of the reliability by shear tests.

In advanced electronic systems, achieving top-tier interconnect interfaces with fine-pitch integration is of paramount importance. Among interconnect options, hybrid bonding is the choice of technology given its exceptional capacity for accommodating a high input/output (I/O) count, which facilitates high-density memory integration, increased power delivery, and enhanced signal speed. One key technique for ensuring utmost quality in hybrid bonding involves embedding Cu interconnects within the dielectric layer. Equally pivotal is surface planarization, accomplished through chemical mechanical polishing (CMP), which combines a two-step procedure, commencing with copper bulk CMP and culminating in barrier CMP. The latter step is particularly critical, yielding the indispensable surface finish required for a successful hybrid bonding process. Several crucial surface properties significantly influence overall bond yield, including a copper recess ("dishing") in the vias, erosion and roughness of the dielectric layer, and surface topography changes from high-density to low-density copper vias. To optimize these parameters, a comprehensive understanding of the interconnect layer's design is essential. Here, we delve into the ramifications of via scaling, ranging from 5 to 1 mu m, on dishing and roll-off, and the effects of copper via density variation, spanning from 16% to 13%, on topography. Furthermore, we explore how incorporation of dummy vias impacts the final surface finish, potentially leading to improved bond yield.

Network-based biocomputation (NBC) relies on accurate guiding of biological agents through nanofabricated channels produced by lithographic patterning techniques. Here, we report on the large-scale, wafer-level fabrication of optimized microfluidic channel networks (NBC networks) using electron-beam lithography as the central method. To confirm the functionality of these NBC networks, we solve an instance of a classical non-deterministic-polynomial-time complete ("NP-complete") problem, the subset-sum problem. The propagation of cytoskeletal filaments, e.g., molecular motor-propelled microtubules or actin filaments, relies on a combination of physical and chemical guiding along the channels of an NBC network. Therefore, the nanofabricated channels have to fulfill specific requirements with respect to the biochemical treatment as well as the geometrical confienement, with walls surrounding the floors where functional molecular motors attach. We show how the material stack used for the NBC network can be optimized so that the motor-proteins attach themselves in functional form only to the floor of the channels. Further optimizations in the nanolithographic fabrication processes greatly improve the smoothness of the channel walls and floors, while optimizations in motor-protein expression and purification improve the activity of the motor proteins, and therefore, the motility of the filaments. Together, these optimizations provide us with the opportunity to increase the reliability of our NBC devices. In the future, we expect that these nanolithographic fabrication technologies will enable production of large-scale NBC networks intended to solve substantially larger combinatorial problems that are currently outside the capabilities of conventional software-based solvers.

In the context of microelectronics, the ongoing trend of reducing interconnect pitch sizes to sub-micron levels presents a burgeoning challenge in die-to-wafer assembly. This challenge reverberates through various critical domains, including memory, logic, and the burgeoning landscapes of 5G and 6G applications. The pursuit of fine pitch integration underscores the paramount importance of achieving precise interconnect alignment. Our research is dedicated to the development of an industrial process capable of facilitating self-aligned assembly in the context of die-to-wafer bonding. Within this manuscript, we elucidate the integration approach made possible by this innovative assembly technique, accompanied by an in-depth exploration of our simulation work, which forecasts critical process parameters for achieving superior alignment accuracy post-placement.Furthermore, we validate the results of our simulations through meticulous experimentation, where we demonstrate alignment accuracy extending to an impressive 100 nanometres. This contribution, nestled within the context of die-to-wafer assembly, holds significance for a range of applications and industries, marking a substantial step towards addressing the challenges posed by shrinking interconnect pitch sizes.

In this work, we present the development of an atomic layer deposition (ALD) process for metallic cobalt. The process operates at low temperatures using dicobalt hexacarbonyl-1-heptyne [Co2(CO)6HC≡CC5H11] and hydrogen plasma. For this precursor an ALD window in the temperature range between 50 and 110 °C was determined with a constant deposition rate of approximately 0.1 Å/cycle. The upper limit of the ALD window is defined by the onset of the decomposition of the precursor. In our case, decomposition occurs at temperatures of 125 °C and above, resulting in a film growth in chemical vapour deposition mode. The lower limit of the ALD window is around 35 °C, where the reduction of the precursor is incomplete. The saturation behaviour of the process was investigated. X-ray photoelectron spectroscopy measurements could show that the deposited cobalt is in the metallic state. The finally established process in ALD mode shows a homogeneous coating at the wafer level.

Hybrid bonding is key to achieving high-quality interconnect interfaces for fine pitch integration. It has an advantage over other types of interconnects as it allows a high I/O count for high-density memory, increased power and improved signal speed. To achieve high-quality hybrid bonding, Cu interconnects are embedded in the dielectric. The surface is planarized using chemical mechanical polishing. The final CMP process is usually a two-step process involving copper bulk CMP and then barrier CMP. Barrier CMP leads to the final surface finish which is used for hybrid bonding. The final surface has four key surface properties such as copper recess in the vias known as dishing, erosion and roughness of the dielectric layer, and profile change from high-density copper vias towards low-density copper vias. Most of these parameters are tuned using the CMP process. In this work, we present the impact of dielectric on the metal CMP process and look into the atomic force microscopy (AFM) dishing and roll-off behaviour of the interconnect vias, scaling down from 5 $\mu \mathrm{m}$ pitch to 1 $\mu \mathrm{m}$ pitch using silicon oxynitride dielectric as the bonding dielectric.

In recent decades, there has been a significant evolution of microelectronic and semiconductor technologies towards the nanoscale. Both bottom-up and top-down integration concepts of functional nanostructures and nanoparticles into micro- and nanofabricated electronic components have become critical issues that decisively affect the performance of smart electronic systems in various application areas such as environmental sensing and energy harvesting. Functional nanostructures and nanoparticles of different shapes, sizes, morphologies, and materials are now used in various technical and industrial applications, medicine, pharmacy, biology, electronics, power engineering, ecology, and many other fields. However, the complex engineering challenge here is the integration of functional nanostructures, such as molecular components (e.g., functional self-assembled molecular monolayers or entities of desoxyribonucleic acid, DNA), organic or inorganic nanoparticles (metal, semiconductor, colloidal materials), or similar building blocks into nanolithographically fabricated environments. Manufacturing paradigms for this integration go beyond current CMOS- and MEMS-fabrication schemes. Scale-bridging and hybrid manufacturing schemes that combine established top-down manufacturing techniques for microelectronic devices, including aspects of nanotechnology, with bottom-up nanoassembly of molecules on unstructured and pre-structured substrates are required. Microsystems technology based on the combination of conventional semiconductor processing with biotechnological approaches has thus become an emerging field with manifold applications, especially in the field of sensor technology. This contribution describes two illustrative and innovative research questions in nanopatterning and system integration at the micro-nano-interface to motivate applications with new and unprecedented functionalities. The first research question focuses on network-based biocomputing (NBC) using biological agents driven by biomolecular motor proteins in a lithographically fabricated nanofluidic channel system. This approach opens up opportunities for energy-efficient solutions to complex mathematical problems as they make their way through the NBC network. Methods are required to create switchable and rewritable nano-networks to address different mathematical problems using a single NBC-chip. Therefore, stimuli-responsive materials must be selectively and locally deposited into the nano-network to control the transport of the filaments through the network. The second research question focuses on nanophotonic devices based on DNA origami. The high-precision arrangement of nanoscopic substructures using specific binding sites (capture ends) of the DNA origami enables the precise arrangement of DNA origami functionalized with individualized metal nanoparticles. This arrangement could be used to exploit individual spectral response mediated by plasmonic effects. From a technological perspective, top-down lithographic nanostructuring technologies and bottom-up nanostructuring technologies are the basis for new device concepts. The adaptability of nanostructures to the world of biological molecules and other nanoscopic building blocks such as quantum dots and nanoparticles enables novel, even personalized, devices and engineering solutions.

Hybrid bonding is one of the key technology to enable solutions for high bandwidth with increasing power and signal integrity. Hybrid bonding involves, face-to-face interconnect formation between wafers and it acts as an extension of fusion bonding technology. Wherein, dielectric materials such as silicon dioxide bond at room temperature and the copper vias embedded in the dielectric expand to form the electrical connections, enabling the interconnect formation between the top and bottom wafer. Hybrid bonding provides advantages over traditional C4 flip-chip bonding involving solder-based micro-bumps, such as, interconnect pitch scaling to less than 10 µm thereby providing higher interconnect density and increased power and signal speed efficiency for memory and high-performance computing application along with better reliability. It is compatible with standard CMOS fabrication technology. In this work, we would like to present the design and process challenges which may lead to improved bonding yield. To enable hybrid bonding with high yield it is necessary that the bonding surfaces are flat with low roughness. The optimized chemical mechanical polishing (CMP) process is one of the key process technology which enables surface topography to be less than 10 nm and surface roughness to be less than 0.8 nm. The surface topography is dependent on the metal via layout, interconnect density and the surrounding dielectrics and hence, these design parameters act as a guiding principle for the application-oriented definition of the design to accommodate different pitch sizes of interconnecting vias (from 1 µm to 10 µm). The mechanical properties of the materials play a key role as well as this will define the removal rate of dielectric and the metals during the CMP process which will affect the dishing and the surface topography. To achieve high bonding yield the surface topography is key as this will affect the bond front propagation and hence the bonded and non-bonded region between the dielectrics. To further improve the bonding yield we have applied a tailored annealing recipe which improves the bonding yield significantly. This paper would focus our work on topography improvement and overall bonding yield in detail and a comparison of bonding yield with and without dummy vias. Dummy vias in this context refer to the copper via structures that are not intended for interconnect formation but are there for CMP process optimization to achieve better process control. Hence, the dummy vias are not connected to the underlying routing metal layer. Figure 1, shows an ideal surface that would result in W2W bonding with high yield. Figure 2 shows, the defects such as high copper dishing, copper protrusion, dielectric erosion and poor surface topography which will result in poor bonding yield. Figure 3 shows the bonding using SiON as the bonding dielectric with (a) without dummy copper vias (~98% bond yield) and (b) with dummy copper vias (~88% bond yield). Figure 1

Flash lamp annealing (FLA) with millisecond pulse durations is reported as a novel curing method for pore precursor's degradation in thin films. A case study on the curing of dielectric thin films is presented. FLA-cured films are being investigated by means of positron annihilation spectroscopy (PAS) and Fourier-transform infrared (FTIR) spectroscopy in order to quantify the nm-scale porosity and post-treatment chemistry, respectively. Results from positron annihilation reveal the onset of the formation of porous voids inside the samples at 6 ms flash treatment time. Moreover, parameter's adjustment (flash duration and energy density) allows for identifying the optimum conditions of effective curing. Within such a systematic investigation, positron results indicate that FLA is able to decompose the porogen (pore precursors) and to generate interconnected (open porosity) or isolated pore networks with self-sealed pores in a controllable way. Furthermore, FTIR results demonstrate the structural evolution after FLA, that help for setting the optimal annealing conditions whereby only a residual amount of porogen remains and at the same time a well-densified matrix, and a hydrophobic porous structures are created. Raman spectroscopy suggests that the curing-induced self-sealing layer developed at the film surface is a graphene oxide-like layer, which could serve as the outside sealing of the pore network from intrusions.